# US 7,411,305 B2 · Interconnect structure encased with high and low k interlevel dielectrics

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- Number: US 7,411,305 B2
- Document ID: US7411305B2
- Status: Granted
- Kind: B2
- Application number: 10/908,359
- Filed: 2005-05-09
- Published: 2006-11-09
- Granted: 2008-08-12
- Earliest claimed: 2005-05-09
- Assignees: International Business Machines Corporation
- Inventors: Steven H. Voldman
- Web page: https://patentgrep.com/patent/US7411305B2

## CPC

- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A structure for improving the electrostatic discharge robustness of an integrated circuit having an electrostatic discharge (ESD) device and a receiver network connected to a pad by interconnects. The interconnect between the pad and the ESD device has a high-k material placed adjacent to at least one surface of the interconnect and extending over the thermal diffusion distance of the interconnect. The high-k material improves the critical current density of the interconnect by increasing the heat capacity and thermal conductivity of the interconnect. The high-k material can be placed on the sides, top and/or bottom of the interconnect. In multiple wire interconnects, the high-k material is placed between the wires of the interconnect. A low-k material is placed beyond the high-k material to reduce the capacitance of the interconnect. The combination of low-k and high-k materials provides an interconnect structure with improved ESD robustness and low capacitance that is well suited for an ESD device. The interconnect to the receiver, which does not carry a high current, is surrounded by a low-k material for reduced capacitance and performance advantages.

## Claims

### Claim 1

A method, comprising:
electrically interconnecting a pad and an electrostatic discharge (ESD) device using an interconnect comprising a plurality of interconnect wires having a common electrical node in a wiring level on a substrate;
substantially filling a high-k material at least in a region in between said interconnect wires, said region extending from a sidewall of one of said interconnect wires to a sidewall of an adjacent one of said interconnect wires; and
placing a low-k material adjacent to the interconnect and located outside of said region that is substantially filled by said high-k material.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the high-k material is disposed between the low-k material and at least one of the interconnect wires and the high-k material has a thickness equal to or greater than a thermal diffusion distance of the interconnect.