# US 7,411,272 B2 · Semiconductor device and method of forming a semiconductor device

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- Number: US 7,411,272 B2
- Document ID: US7411272B2
- Status: Granted
- Kind: B2
- Application number: 11/174,605
- Filed: 2005-07-06
- Published: 2005-11-03
- Granted: 2008-08-12
- Earliest claimed: 2000-09-21
- Assignees: Cambridge Semiconductor Limited
- Inventors: Florin Udrea; Gehan A. J. Amaratunga
- Web page: https://patentgrep.com/patent/US7411272B2

## CPC

- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 12/01: Manufacture or treatment
- H10D 12/032: {of vertical IGBTs}
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/411: {Insulated-gate bipolar transistors [IGBT]}
- H10D 12/421: {on insulating layers or insulating substrates, e.g. thin-film IGBTs}
- H10D 12/441: {Vertical IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/64: Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D 30/657: {having substrates comprising insulating layers, e.g. SOI-LDMOS transistors}
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/667: {having substrates comprising insulating layers, e.g. SOI-VDMOS transistors}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/104: {having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 62/141: {Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs}
- H10W 10/021: {of air gaps}
- H10W 10/20: Air gaps
- H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/8325: {Silicon carbide}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/516: {the thicknesses being non-uniform}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

## Claims

### Claim 1

A lateral power semiconductor device having an active region that includes a drift region, at least a portion of the drift region being provided in a membrane having opposed top and bottom surfaces, the top surface of the membrane having electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region, the lateral power semiconductor device being constructed and arranged such that, when the lateral power semiconductor device is an off-state and operating in a voltage-blocking mode, the equi-potential lines within said at least a portion of the drift region are all substantially perpendicular to the top and bottom surfaces of the membrane and are substantially uniformly distributed across said at least a portion of the drift region so that the electric field across said at least a portion of the drift region is substantially uniform.

### Claim 2 (depends on 1)

A lateral power semiconductor device according to claim 1, wherein only part of the drift region is provided in the membrane.

### Claim 3 (depends on 1)

A lateral power semiconductor device according to claim 1, wherein the whole of the drift region is provided in the membrane.

### Claim 4 (depends on 1)

A lateral power semiconductor device according to claim 1, comprising at least one isolation layer surrounding the drift region.

### Claim 5 (depends on 1)

A lateral power semiconductor device according to claim 1, comprising at least one isolation layer surrounding the drift region and provided outside the membrane.

### Claim 6 (depends on 1)

A lateral power semiconductor device according to claim 1, and further comprising at least one additional power device having a drift region at least a portion of which is provided on said membrane or on a separate membrane.

### Claim 7

A power integrated circuit, comprising:
a lateral power semiconductor device having an active region that includes a drift region, at least a portion of the drift region being provided in a membrane having opposed top and bottom surfaces, the top surface of the membrane having electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region, the lateral power semiconductor device being constructed and arranged such that, when the lateral power semiconductor device is an off-state and operating in a voltage-blocking mode, the equi-potential lines within said at least a portion of the drift region are all substantially perpendicular to the top and bottom surfaces of the membrane and are substantially uniformly distributed across said at least a portion of the drift region so that the electric field across said at least a portion of the drift region is substantially uniform; and
at least one low voltage device.

### Claim 8 (depends on 1)

A lateral power semiconductor device according to claim 1, wherein the membrane comprises a semiconductor layer provided on an electrically insulating layer.

### Claim 9 (depends on 1)

A lateral power semiconductor device according to claim 1, comprising a mechanically strong and electrically insulating layer provided under the membrane.

### Claim 10 (depends on 1)

A lateral power semiconductor device according to claim 1, wherein the drift region has a non-uniform doping profile.

### Claim 11 (depends on 10)

A lateral power semiconductor device according to claim 10, wherein the doping concentration of the drift region at a high voltage terminal side of the lateral power semiconductor device is relatively high and the doping concentration of the drift region at a low voltage terminal side of the lateral power semiconductor device is relatively low.

### Claim 12 (depends on 10)

A lateral power semiconductor device according to claim 10, wherein the doping concentration of the drift region varies linearly from one side of the drift region to the other.

### Claim 13 (depends on 1)

A lateral power semiconductor device according to claim 1, wherein the drift region comprises at least two semiconductor layers of alternating conductivity type arranged one above the other and in contact with each other.

### Claim 14 (depends on 1)

A lateral power semiconductor device according to claim 1, wherein the drift region comprises a plurality of laterally adjacent semiconductor regions of alternating conductivity type.

### Claim 15 (depends on 1)

A lateral power semiconductor device according to claim 1, comprising a termination region adjacent to and in contact with the drift region, said termination region being provided to reduce the effect of premature breakdown at the edge of the drift region.

### Claim 16 (depends on 15)

A lateral power semiconductor device according to claim 15, wherein at least a portion of the said termination region is placed inside the membrane.

### Claim 17 (depends on 15)

A lateral power semiconductor device according to claim 15, wherein at least a portion of the said termination region is placed outside the membrane.