# US 7,411,269 B2 · Isolation structure configurations for modifying stresses in semiconductor devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,411,269 B2 - Document ID: US7411269B2 - Status: Granted - Kind: B2 - Application number: 11/091,967 - Filed: 2005-03-28 - Published: 2005-08-18 - Granted: 2008-08-12 - Earliest claimed: 1999-08-13 - Assignees: Intel Corporation - Inventors: Qing Ma; Jin Lee; Harry Fujimoto; Changhong Dai; Shiuh-Wuu Lee; Travis Eiles; Krishna Seshan - Web page: https://patentgrep.com/patent/US7411269B2 ## CPC - H10D 30/791: {Arrangements for exerting mechanical stress on the crystal lattice of the channel regions} - H10D 30/795: {being in lateral device isolation regions, e.g. STI} - H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10W 72/884: {Die-attach connectors and bond wires} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device. ## Claims ### Claim 1 A semiconductor device, comprising: an active area formed in a semiconductor substrate; and an isolation structure formed in said semiconductor substrate and around said active area, wherein said isolation structure comprises a first region coupled with and perpendicular to a second region, wherein said first region and said second region are in the same plane of said semiconductor substrate, and wherein the modulus of said first region is different than the modulus of said second region. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein said active area further comprises nMOS device components including an n-type source region, an n-type drain region, and a gate structure disposed adjacent said active area between said n-type source region and said n-type drain region. ### Claim 3 (depends on 2) The semiconductor device of claim 2, wherein said first region substantially comprises a low-modulus, dielectric material. ### Claim 4 (depends on 2) The semiconductor device of claim 2, wherein said first region substantially comprises a tensile stress-inducing, dielectric material. ### Claim 5 (depends on 2) The semiconductor device of claim 2, wherein said active area includes a width and wherein said first region has a depth such that an aspect ratio of said depth to said active area width is greater than about 0.5. ### Claim 6 (depends on 5) The semiconductor device of claim 5, wherein said first region substantially comprises a low-modulus, dielectric material. ### Claim 7 (depends on 5) The semiconductor device of claim 5, wherein said first region substantially comprises a tensile stress-inducing, dielectric material. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein said active area further comprises pMOS device components including a p-type source region, a p-type drain region, and a gate structure disposed adjacent said active area between said p-type source region and said p-type drain region. ### Claim 9 (depends on 8) The semiconductor device of claim 8, wherein said first region substantially comprises a low-modulus, dielectric material, and wherein said first region is parallel to a channel current direction of the pMOS device components. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein said second region substantially comprises a high-modulus, dielectric material, and wherein said second region is perpendicular to the channel current direction of the pMOS device components. ### Claim 11 (depends on 8) The semiconductor device of claim 8, wherein said first region substantially comprises a low-modulus, dielectric material, and wherein said first region is perpendicular to a channel current direction of the pMOS device components. ### Claim 12 (depends on 11) The semiconductor device of claim 11, wherein said second region substantially comprises a high-modulus, dielectric material, and wherein said second region is parallel to the channel current direction of the pMOS device components. ### Claim 13 (depends on 8) The semiconductor device of claim 8, wherein said first region substantially comprises a tensile stress-inducing, dielectric material, and wherein said first region is parallel to the channel current direction of the pMOS device components. ### Claim 14 (depends on 8) The semiconductor device of claim 8, wherein said first region substantially comprises a compressive stress-inducing, dielectric material, and wherein said first region is perpendicular to the channel current direction of the pMOS device components. ### Claim 15 (depends on 8) The semiconductor device of claim 8, wherein said first region has a depth and is parallel to a channel current direction of the pMOS device components, and wherein said active area includes a width such that an aspect ratio of said depth to said active area width is greater than about 0.5. ### Claim 16 (depends on 15) The semiconductor device of claim 15, wherein said first region substantially comprises a low-modulus, dielectric material. ### Claim 17 (depends on 15) The semiconductor device of claim 15, wherein said first region substantially comprises a tensile stress-inducing, dielectric material. ### Claim 18 (depends on 15) The semiconductor device of claim 15, wherein said second region substantially comprises a high-modulus, dielectric material, and wherein said second region is perpendicular to the channel current direction of the pMOS device components. ### Claim 19 (depends on 15) The semiconductor device of claim 15, wherein said second region substantially comprises a compressive stress-inducing, dielectric material, and wherein said second region is perpendicular to the channel current direction of the pMOS device components. ### Claim 20 (depends on 8) The semiconductor device of claim 8, wherein said active area includes a width and wherein said first region is perpendicular to a channel current direction of the pMOS device components and has a depth such that an aspect ratio of said depth to said active area width is greater than about 0.5. ### Claim 21 (depends on 20) The semiconductor device of claim 20, wherein said first region substantially comprises a low-modulus, dielectric material. ### Claim 22 (depends on 20) The semiconductor device of claim 20, wherein said first region substantially comprises a compressive stress-inducing, dielectric material. ### Claim 23 (depends on 20) The semiconductor device of claim 20, wherein said second region substantially comprises a high-modulus, dielectric material, and wherein said second region is parallel to the channel current direction of the pMOS device components. ### Claim 24 (depends on 20) The semiconductor device of claim 20, wherein said second region substantially comprises a tensile stress-inducing, dielectric material, and wherein said second region is parallel to the channel current direction of the pMOS device components.