Substrate backgate for trigate FET

A field effect transistor comprising:

• a semiconductor substrate, having a first conductivity type;
• a fin on said semiconductor substrate,
• wherein said fin comprises:
• an upper semiconductor portion, having said first conductivity type;
• and,
• a lower back gate portion, and w
• herein said lower back gate portion comprises:
• a back gate dielectric layer below said upper semiconductor portion;
• and
• a back gate electrode between said semiconductor substrate and said back gate dielectric layer;
• a front gate adjacent a top surface and opposing sidewalls of said upper semiconductor portion of said fin and electrically isolated from said back gate electrode and from said semiconductor substrate;
• and,
• a well, having a second conductivity type different from said first conductivity type, in said semiconductor substrate below said lower back gate portion of said fin, wherein said back gate electrode is in contact with said well.

A field effect transistor comprising:

• a substrate;
• a fin on said substrate,
• wherein said fin comprises:
• an upper semiconductor portion;
• and,
• a lower back gate portion, and
• wherein said lower back gate portion comprises:
• a back gate dielectric layer below said upper semiconductor portion;
• and
• a back gate electrode between said substrate and said back gate dielectric layer;
• and,
• a front gate adjacent a top surface and opposing sidewalls of said upper semiconductor portion of said fin and electrically isolated from said back gate electrode, wherein said back gate electrode comprises one of silicon germanium and silicon germanium carbide, and
• wherein said back gate electrode has a designated conductivity type.

A field effect transistor comprising:

• a semiconductor substrate, having a first conductivity type;
• a fin on said semiconductor substrate,
• wherein said fin comprises:
• an upper semiconductor portion, having said first conductivity type;
• and,
• a lower back gate portion, and
• wherein said lower back gate portion comprises:
• a back gate dielectric layer below said upper semiconductor portion;
• and
• a back gate electrode between said semiconductor substrate and said back gate dielectric layer, wherein said back gate electrode has a second conductivity type different from said first conductivity type;
• an additional dielectric layer on said semiconductor substrate and on opposing sidewalls of said back gate electrode;
• a front gate above said additional dielectric layer and further adjacent said upper semiconductor portion of said fin such that said additional dielectric layer electrically isolates said front gate from said back gate electrode and from said semiconductor substrate;
• and,
• a well, having said second conductivity type, in said semiconductor substrate below said lower back gate portion of said fin, wherein said back gate electrode is in contact with said well.