# US 7,411,250 B2 · Radiation-hardened silicon-on-insulator CMOS device, and method of making the same

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- Number: US 7,411,250 B2
- Document ID: US7411250B2
- Status: Granted
- Kind: B2
- Application number: 10/846,864
- Filed: 2004-05-13
- Published: 2005-01-13
- Granted: 2008-08-12
- Earliest claimed: 2001-04-05
- Assignees: Peregrine Semiconductor Corporation
- Inventors: Anthony M. Miscione; George Imthurn; Eugene F. Lyons; Michael A. Stuber
- Web page: https://patentgrep.com/patent/US7411250B2

## CPC

- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D 86/03: wherein the substrate comprises sapphire, e.g. silicon-on-sapphire [SOS]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A silicon-on-insulator metal oxide semiconductor device comprising ultrathin silicon-on-sapphire substrate; at least one P-channel MOS transistor formed in the ultrathin silicon layer; and N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration in the sapphire layer is greater than peak impurity concentration in the ultrathin silicon layer.

## Claims

### Claim 1

A silicon-on-insulator metal oxide semiconductor device comprising:
an ultrathin silicon layer on a sapphire substrate;
at least one P-channel MOS transistor formed in the ultrathin silicon layer;
N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration in the sapphire substrate is at least 10 times greater than peak impurity concentration in the ultrathin silicon layer.

### Claim 2 (depends on 1)

The device of claim 1,
wherein the N-type impurity implanted within the sapphire substrate has a peak concentration disposed at least 0.05 microns from a silicon-sapphire back interface.

### Claim 3 (depends on 1)

The device of claim 1,
wherein the peak N-type impurity concentration within the sapphire substrate is approximately 1.0×1019 ions/cm2.

### Claim 4

A silicon-on-insulator metal oxide semiconductor device comprising:
an ultrathin silicon layer on a sapphire substrate;
at least one P-channel MOS transistor formed in the ultrathin silicon layer;
N-type impurity implanted within the sapphire substrate such that peak N-type impurity concentration within the sapphire substrate is disposed at least 0.05 microns from a silicon-sapphire back interface.

### Claim 5 (depends on 4)

The device of claim 4,
wherein the N-type impurity implanted within the sapphire substrate has a peak impurity concentration disposed at least 0.10 microns from a silicon-sapphire back interface.

### Claim 6 (depends on 4)

The device of claim 4,
wherein the peak N-type impurity concentration within the sapphire substrate is approximately 1.0×1019 ions/cm2.

### Claim 7

A silicon-on-insulator metal oxide semiconductor device comprising:
an ultrathin silicon layer on a sapphire substrate;
at least one P-channel MOS transistor formed in the ultrathin silicon layer;
N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration of approximately 1.0×1019 ions/cm2in the sapphire layer, which is at least 10 times greater than peak impurity concentration in the ultrathin silicon layer and which is disposed at least 0.05 microns from a silicon-sapphire back interface.

### Claim 8

A silicon-on-insulator metal oxide semiconductor device comprising:
an ultrathin silicon layer on a sapphire substrate;
at least one P-channel MOS transistor formed in the ultrathin silicon layer;
wherein the ultrathin silicon layer is characterized by a retrograde N-type dopant concentration profile in the P-channel region;
wherein the sapphire substrate is characterized by a retrograde N-type dopant concentration in the sapphire substrate opposite the P-channel region; and
wherein peak N-type dopant concentration is at least 10 times higher in the sapphire substrate than peak N-type dopant concentration in the P-channel region.

### Claim 9 (depends on 8)

The device of claim 8 further including:
an interface region in which the ultrathin silicon layer adjoins the sapphire substrate;
wherein the retrograde N-type dopant concentration profile in the P-channel region the retrograde N-type dopant concentration profile in the sapphire substrate opposite the P-channel region together form a retrograde N-type dopant concentration profile across the P-channel region, the interface region and the sapphire substrate opposite the P-channel region.

### Claim 10 (depends on 8)

The device of claim 8,
an interface region in which the ultrathin silicon layer adjoins the sapphire substrate;
wherein the retrograde N-type dopant concentration in the sapphire substrate increases with increasing distance from the interface region up to a peak concentration region and trails off after the peak concentration region, with increasing distance from the interface region.

### Claim 11

A silicon-on-insulator metal oxide semiconductor device comprising:
an ultrathin silicon layer on a sapphire substrate;
at least one P-channel MOS transistor formed in the ultrathin silicon layer;
wherein the ultrathin silicon layer is characterized by a retrograde N-type dopant concentration profile in the P-channel region;
wherein the sapphire substrate is characterized by a retrograde N-type dopant concentration in the sapphire substrate opposite the P-channel region; and
wherein peak N-type dopant concentration is in the sapphire substrate and is disposed at least 0.05 microns from a silicon-sapphire back interface.

### Claim 12 (depends on 11)

The device of claim 11 further including:
an interface region in which the ultrathin silicon layer adjoins the sapphire substrate;
wherein the retrograde N-type dopant concentration profile in the P-channel region the retrograde N-type dopant concentration profile in the sapphire substrate opposite the P-channel region together form a retrograde N-type dopant concentration profile across the P-channel region, the interface region and the sapphire substrate opposite the P-channel region.

### Claim 13 (depends on 11)

The device of claim 11,
an interface region in which the ultrathin silicon layer adjoins the sapphire substrate;
wherein the retrograde N-type dopant concentration in the sapphire substrate increases with increasing distance from the interface region up to a peak concentration region and trails off after the peak concentration region, with increasing distance from the interface region.

### Claim 14 (depends on 1)

The device of claim 1 further including:
an N-type threshold voltage setting implant in the P-channel region.

### Claim 15 (depends on 1)

The device of claim 1 further including:
an interface region in which the ultrathin silicon layer adjoins the sapphire substrate;
wherein the retrograde N-type dopant concentration profile in the P-channel region is substantially continuous with the retrograde N-type dopant concentration profile in the sapphire substrate opposite the P-channel region so as to form a substantially continuous N-type dopant concentration profile across the P-channel region, the interface region and the sapphire substrate opposite the P-channel region;
wherein the retrograde N-type dopant concentration in the sapphire substrate increases with increasing distance from the interface region up to a peak concentration region, which is at prescribed distance from the interface region, and trails off after the peak concentration region, with increasing distance from the interface region; and
wherein the prescribed distance is selected to be far enough from the interface region that radiation-induced charge that may become trapped does not produce an inversion region near the interface region.

### Claim 16 (depends on 1, 4)

A device according to claim 1 or 4,
wherein the N-channel dopant is selected from the group consisting of phosphorous, arsenic and antimony.

### Claim 17 (depends on 1, 4)

A device according to claim 1 or 4 further including:
an N-channel device interconnected with the P-channel device to from a CMOS device.

### Claim 18 (depends on 1, 4)

The device of claim 1 or 4,
wherein respective source and drain regions of the P-channel device extend to a silicon-sapphire interface.