# US 7,411,244 B2 · Low power electrically alterable nonvolatile memory cells and arrays

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- Number: US 7,411,244 B2
- Document ID: US7411244B2
- Status: Granted
- Kind: B2
- Application number: 11/234,646
- Filed: 2005-09-23
- Published: 2006-12-28
- Granted: 2008-08-12
- Earliest claimed: 2005-06-28
- Inventors: Chih-Hsin Wang
- Web page: https://patentgrep.com/patent/US7411244B2

## CPC

- H10B 43/30: characterised by the memory core region
- H10B 41/30: characterised by the memory core region
- H10B 43/10: characterised by the top-view layout
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling}
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10D 30/6894: {having one gate at least partly in a trench}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/64: Electrodes comprising a Schottky barrier to a semiconductor
- H10P 30/221: {characterised by the angle between the ion beam and the mask}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- G11C 16/0416: {comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM}
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Nonvolatile memory cells having a conductor-filter system, a conductor-insulator system, and a charge-injection system are provided. The conductor-filter system provides band-pass filtering function, charge-filtering function, and mass-filtering function to charge-carriers flows. The conductor-insulator system provides Image-Force barrier lowering effect to collect charge-carriers. The charge-injection system includes the conductor-filter system and the conductor-insulator system, wherein the filter of the conductor-filter system contacts the conductor of the conductor-insulator system. Apparatus on cell architecture are provided for the nonvolatile memory cells. Additionally, apparatus on array architectures are provided for constructing the nonvolatile memory cells in memory array. Method on manufacturing such memory cells and array architectures are provided.

## Claims

### Claim 1

A memory cell comprising:
a body of a semiconductor material having a first conductivity type;
a conductor-filter system including:
a first conductor having thermal charge carriers; and
a filter contacting the first conductor and including dielectrics for providing a filtering function on the charge carriers of one polarity, wherein the filter includes:
a first set of electrically alterable potential barriers for controlling flow of the charge carriers of one polarity through the filter in one direction;
a conductor-insulator system including:
a second conductor having at least a portion thereof contacting the filter and having energized charge carriers from the filter; and
a first insulator contacting the second conductor at an interface and having electrically alterable Image-Force potential barriers adjacent to the interface;
a first region spaced-apart from the second conductor with a channel of the body defined there between;
a second insulator adjacent to the first region;
a charge storage region disposed in between the first and the second insulators; and
a word-line of a conductor having:
a first portion disposed over and insulated from the charge storage region, and
a second portion comprising the first conductor disposed over and insulated from the body.

### Claim 2 (depends on 1)

The memory cell of claim 1, wherein the filter further includes a second set of electrically alterable potential barriers for controlling flow of charge carriers of an opposite polarity through the filter in another direction that is substantially opposite to the one direction.

### Claim 3 (depends on 1)

The memory cell of claim 1, wherein the filter comprises:
a first dielectric disposed adjacent to the first conductor and having an energy band gap; and
a second dielectric disposed adjacent to the first dielectric, wherein the second dielectric has an energy band gap narrower than the energy band gap of the first dielectric.

### Claim 4 (depends on 3)

The memory cell of claim 3, wherein the first dielectric has a first dielectric constant and the second dielectric has a dielectric constant that is substantially greater than the first dielectric constant.

### Claim 5 (depends on 3)

The memory cell of claim 3, wherein the first dielectric has a first dielectric constant and a first thickness and the second dielectric has a second dielectric constant and a second thickness, and wherein a product of the second dielectric constant and the first thickness is substantially greater than a product of the first dielectric constant and the second thickness.

### Claim 6 (depends on 3)

The memory cell of claim 3, wherein the first dielectric comprises oxide having a thickness in a range of about 1.5 nm to about 4 nm, and the second dielectric comprises material selected from the group consisting of nitride, oxynitride, Al2O3, HfO2, TiO2, ZrO2, Ta2O5, and alloys formed thereof.

### Claim 7 (depends on 3)

The memory cell of claim 3, wherein the first dielectric comprises oxynitride having a thickness in a range of about 1.5 nm to about 4 nm, and the second dielectric comprises material selected from the group consisting of nitride, Al2O3, HfO2, TiO2, ZrO2, Ta2O5, and alloys formed thereof.

### Claim 8 (depends on 1)

The memory cell of claim 1, wherein the charge storage region comprises conductive material having a larger work-function than a work-function of the second conductor.

### Claim 9 (depends on 8)

The memory cell of claim 8, wherein the charge storage region comprises p-type polysilicon and the second conductor comprises n-type silicon.

### Claim 10 (depends on 1)

The memory cell of claim 1, wherein the first region comprises a semiconductor material having a second conductivity type.

### Claim 11 (depends on 1)

The memory cell of claim 1, wherein the second conductor comprises a semiconductor material having a second conductivity type.

### Claim 12 (depends on 1)

The memory cell of claim 1, wherein the body comprises silicon, and the first region and the second conductor comprises a semiconductor material selected from the group including silicon, and SiGe.

### Claim 13 (depends on 1)

The memory cell of claim 1, wherein the first region comprises a first connector and a first junction.

### Claim 14 (depends on 13)

The memory cell of claim 13, wherein the first connector and the first junction are formed in a self-aligned manner.

### Claim 15 (depends on 13)

The memory cell of claim 13, wherein the first junction comprises junction selected from the group consisting of p-n junction and Schottky junction.

### Claim 16 (depends on 13)

The memory cell of claim 13, wherein the first connector comprises material selected from the group including polysilicon, poly-SiGe, SiGe, Al, Pt, Au, W, Mo, Ru, Ta, Ni, TaN, TiN, platinum-silicide, titanium silicide, tungsten-silicide, tungsten-polycide, nickel-silicide, cobalt-silicide, erbium silicide, terbium silicide, dysprosium silicide, and ytterbium silicide.

### Claim 17 (depends on 1)

The memory cell of claim 1, wherein the second conductor comprises a second connector and a second junction.

### Claim 18 (depends on 17)

The memory cell of claim 17, wherein the second connector and the second junction are formed in a self-aligned manner.

### Claim 19 (depends on 17)

The memory cell of claim 17, wherein the second junction comprises junction selected from the group consisting of p-n junction and Schottky junction.

### Claim 20 (depends on 17)

The memory cell of claim 17, wherein the second connector comprises material selected from the group including polysilicon, poly-SiGe, SiGe, Al, Pt, Au, W, Mo, Ru, Ta, Ni, TaN, TiN, platinum-silicide, titanium silicide, tungsten-silicide, tungsten-polycide, nickel-silicide, cobalt-silicide, erbium silicide, terbium silicide, dysprosium silicide, and ytterbium silicide.

### Claim 21 (depends on 1)

The memory cell of claim 1, wherein the word-line comprises material selected from the group including n+ polysilicon, p+ polysilicon, poly-SiGe, Al, Pt, Au, W, Mo, Ru, Ta, Ni, TaN, TiN, and alloy formed thereof.

### Claim 22 (depends on 1)

The memory cell of claim 1, further comprising a buried well of a semiconductor material having a second conductivity type and disposed in between the body and a substrate.

### Claim 23 (depends on 1)

The memory cell of claim 1, wherein the energized charge carriers has an energy distribution with an energy spectrum in the range of about 30 meV to about 300 meV.

### Claim 24 (depends on 1)

The memory cell of claim 1, wherein the first and the second insulators comprise dielectrics of the oxynitride system SiOxN1-x.

### Claim 25 (depends on 1)

The memory cell of claim 1, wherein a thickness of the second insulator is thinner than a thickness of the first insulator.

### Claim 26

A memory cell comprising:
a body of a semiconductor material having a first conductivity type;
a conductor-filter system including:
a first conductor having thermal charge carriers; and
a filter contacting the first conductor and including dielectrics for providing a filtering function on the charge carriers of one polarity, wherein the filter includes:
a first set of electrically alterable potential barriers for controlling flow of the charge carriers of one polarity through the filter in one direction, and
a second set of electrically alterable potential barriers for controlling flow of charge carriers of an opposite polarity through the filter in another direction that is substantially opposite to the one direction;
a conductor-insulator system including:
a second conductor having at least a portion thereof contacting the filter and having energized charge carriers from the filter; and
a first insulator contacting the second conductor at an interface and having electrically alterable Image-Force potential barriers adjacent to the interface;
a first region spaced-apart from the second conductor with a channel of the body defined there between;
a second insulator adjacent to the first region;
a charge storage region disposed in between the first and the second insulators;
a word-line of a conductor having:
a first portion disposed over and insulated from the charge storage region, and
a second portion comprising the first conductor disposed over and insulated from the body; and
means for transporting the energized charge carriers over the Image-Force potential barrier onto the charge storage region.

### Claim 27 (depends on 26)

The memory cell of claim 26, wherein the means is the ballistic-hole injection mechanism and wherein the energized charge carriers are ballistic light-holes.

### Claim 28 (depends on 26)

The memory cell of claim 26, wherein the means is the ballistic-electron injection mechanism and wherein the energized charge carriers are ballistic electrons.

### Claim 29 (depends on 26)

The memory cell of claim 26, wherein the energized charge carriers has an energy distribution with an energy spectrum in the range of about 30 meV to about 300 meV.

### Claim 30

A nonvolatile memory array comprising:
a substrate;
a plurality of nonvolatile memory cells on the substrate, and arranged in a rectangular array of rows and columns, each of the plurality of nonvolatile memory cells comprising:
a body of a semiconductor material having a first conductivity type;
a conductor-filter system including:
a first conductor having thermal charge carriers; and
a filter contacting the conductor and including dielectrics for providing a filtering function on the charge carriers of one polarity, wherein the filter includes:
a first set of electrically alterable potential barriers for controlling flow of the charge carriers of one polarity through the filter in one direction, and
a second set of electrically alterable potential barriers for controlling flow of charge carriers of an opposite polarity through the filter in another direction that is substantially opposite to the one direction;
a conductor-insulator system including:
a second conductor having at least a portion thereof contacting the filter and having energized charge carriers from the filter; and
a first insulator contacting the second conductor at an interface and having electrically alterable Image-Force potential barriers adjacent to the interface;
a first region spaced-apart from the second conductor with a channel of the body defined there between;
a second insulator adjacent to the first region;
a charge storage region disposed in between the first and the second insulators; and
a third conductor having:
a first portion disposed over and insulated from the charge storage region, and
a second portion comprising the first conductor disposed over and insulated from the body.

### Claim 31 (depends on 30)

The nonvolatile memory array of claim 30, further comprising:
a plurality of word-lines oriented in a first direction;
a plurality of source-lines oriented in a second direction; and
a plurality of bit-lines oriented in the second direction,
wherein each of the word-lines connects the third conductor of each of the memory cells in a same row, each of the bit-lines connects the second conductor of each of the memory cells in a same column, and each of the source-lines connects the first region of each of the memory cells in a same column.

### Claim 32 (depends on 30)

The nonvolatile memory array of claim 30, wherein the memory cells are formed as pairs of memory cells having each of the memory cell pairs sharing a single first region therebetween.

### Claim 33 (depends on 30)

The nonvolatile memory array of claim 30, wherein the memory cells are formed as pairs of memory cells, and wherein one cell of one cell pair in one column and one cell of another cell pair in a same row and in an adjacent column shares a single first conductor therebetween.

### Claim 34 (depends on 30)

The nonvolatile memory array of claim 30, wherein the substrate comprises a semiconductor material having a first conductivity type, and the nonvolatile memory array further comprising a buried well of a semiconductor material having a second conductivity type disposed in between the body of each of memory cells and the substrate.