# US 7,411,243 B2 · Nonvolatile semiconductor device and method of fabricating the same

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- Number: US 7,411,243 B2
- Document ID: US7411243B2
- Status: Granted
- Kind: B2
- Application number: 11/214,247
- Filed: 2005-08-29
- Published: 2006-03-02
- Granted: 2008-08-12
- Earliest claimed: 2004-08-27
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Young-Sam Park; Seung-Beom Yoon; Jeong-Uk Han; Sung-Taeg Kang; Seung-Jin Yang
- Web page: https://patentgrep.com/patent/US7411243B2

## CPC

- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6213: {having rounded corners}
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A nonvolatile semiconductor device and a method of fabricating the same are provided. The nonvolatile semiconductor device includes a semiconductor body formed on a substrate to be elongated in one direction and having a cross section perpendicular to a main surface of the substrate and elongated direction, the cross section having a predetermined curvature, a channel region partially formed along the circumference of the semiconductor body, a tunneling insulating layer disposed on the channel region, a floating gate disposed on the tunneling insulating layer and electrically insulated from the channel region, an intergate insulating layer disposed on the floating gate, a control gate disposed on the intergate insulating layer and electrically insulated from the floating gate, and source and drain regions which are aligned with both sides of the control gate and formed within the semiconductor body.

## Claims

### Claim 1

A nonvolatile semiconductor device comprising:
a semiconductor body formed on a substrate, elongated in one direction and having a cross section perpendicular to a main surface of the substrate and to the elongated direction, the cross section having a predetermined curvature;
a channel region partially formed on the semiconductor body along the circumference of the semiconductor body;
a tunneling insulating layer disposed on the channel region;
a floating gate disposed on the tunneling insulating layer and electrically insulated from the channel region;
an intergate insulating layer disposed on the floating gate;
a control gate disposed on the intergate insulating layer and electrically insulated from the floating gate; and
source and drain regions which are adjacent to sides of the control gate and formed on the semiconductor body.

### Claim 2 (depends on 1)

The nonvolatile semiconductor device of claim 1, wherein the semiconductor body is shaped in a semi-circle, a circle or an oval.

### Claim 3 (depends on 1)

The nonvolatile semiconductor device of claim 1, wherein the predetermined curvature of the cross section of the semiconductor body is irregular.

### Claim 4 (depends on 1)

The nonvolatile semiconductor device of claim 1, wherein the substrate is a bulk substrate.

### Claim 5 (depends on 4)

The nonvolatile semiconductor device of claim 4, further comprising device isolation regions disposed at both sides of a lower portion of the semiconductor body to define a region of the semiconductor body.

### Claim 6 (depends on 5)

The nonvolatile semiconductor device of claim 5, wherein the semiconductor body is formed on a semiconductor fin interposed between the device isolation regions and filling a portion of a space between the device isolation regions.

### Claim 7 (depends on 1)

The nonvolatile semiconductor device of claim 1, wherein the substrate is a silicon-on-insulator (SOI) substrate.

### Claim 8 (depends on 7)

The nonvolatile semiconductor device of claim 7, wherein the semiconductor body is disposed over a buried oxide film of the SOI substrate.

### Claim 9 (depends on 8)

The nonvolatile semiconductor device of claim 8, wherein the semiconductor body includes a silicon fin formed on the substrate and a semiconductor layer formed on the silicon fin by a selective epitaxial growth method.

### Claim 10 (depends on 1)

The nonvolatile semiconductor device of claim 1, wherein the substrate is made of Si, Ge, SiGe, GaAs, SiC, SiGeC, InAs, InP or a combination thereof.

### Claim 11 (depends on 1)

The nonvolatile semiconductor device of claim 1, wherein the semiconductor body is made of Si, Ge, Si1-xGex (0<x<1), Si1-xCx (0<x<1), Si1-x-yGexCy (0<x<1, 0<y<1), GaAs, InSb, GaP or a combination thereof.

### Claim 12 (depends on 1)

The nonvolatile semiconductor device of claim 1, wherein the semiconductor body is formed of a plurality of semiconductor layers having different band gaps.

### Claim 13 (depends on 1)

The nonvolatile semiconductor device of claim 1, wherein the floating gate is made of n+ polysilicon, p+ polysilicon, SiGe having a changeable work function, a metallic material or a combination thereof.

### Claim 14 (depends on 1)

The nonvolatile semiconductor device of claim 1, wherein the tunneling insulating layer is an oxide layer, the floating gate is a nitride layer (Si3N4), and the intergate insulating layer is an oxide layer.

### Claim 15 (depends on 1)

The nonvolatile semiconductor device of claim 1, further comprising a blocking insulating layer formed between the substrate and the semiconductor body to define a contact region.

### Claim 16 (depends on 15)

The nonvolatile semiconductor device of claim 15, wherein the blocking insulating layer is shaped in the form of a spacer for covering sidewalls of the device isolation regions.

### Claim 17 (depends on 1)

The nonvolatile semiconductor device of claim 1, wherein the control gate surrounds the circumference of the semiconductor body.

### Claim 18 (depends on 1)

The nonvolatile semiconductor device of claim 1, wherein the semiconductor body is formed over an oxide layer fin formed on the substrate, the floating gate is formed on the tunneling insulating layer and a sidewall of the oxide layer fin, and the control gate is formed along the intergate insulating layer and an upper portion of the substrate.

### Claim 19 (depends on 18)

The nonvolatile semiconductor device of claim 18, wherein the substrate is a silicon-on-insulator (SOI) substrate.

### Claim 20 (depends on 19)

The nonvolatile semiconductor device of claim 19, wherein the oxide layer fin is formed by etching a buried oxide film of the SOI substrate.

### Claim 21 (depends on 18)

The nonvolatile semiconductor device of claim 18, wherein the floating gate is made of at least one selected from the group consisting of n+ polysilicon, p+ polysilicon, SiGe having a changeable work function, a metallic material and a nitride layer (Si3N4).

### Claim 22 (depends on 18)

The nonvolatile semiconductor device of claim 18, wherein the tunneling insulating layer is an oxide layer, the floating gate is a nitride layer (Si3N4), and the intergate insulating layer is an oxide layer.

### Claim 23 (depends on 18)

The nonvolatile semiconductor device of claim 18, wherein the control gate surrounds the circumference of the semiconductor body.

### Claim 24

A method of fabricating a nonvolatile semiconductor device comprising:
forming a semiconductor body on a substrate, elongated in one direction and having a cross section perpendicular to a main surface of the substrate and to the elongated direction, the cross section having a predetermined curvature; forming a tunneling insulating layer on the semiconductor body;
forming a floating gate, which is electrically insulated from the semiconductor body, on the tunneling insulating layer;
forming an intergate insulating layer on the floating gate;
forming a control gate, which is electrically insulated from the floating gate, on the intergate insulating layer; and
forming source and drain regions, which are aligned with both sides of the control gate, within the semiconductor body.

### Claim 25 (depends on 24)

The method of claim 24, wherein the forming of the semiconductor body comprises:
forming the semiconductor body, which contains channels formed on a plurality of planes, by a selective epitaxial growth method using a semiconductor fin formed on the substrate as a seed layer; and
performing an annealing process on the semiconductor body so that the semiconductor body has a cross section of the perpendicular to a main surface of the substrate and elongated direction, the cross section having a predetermined curvature.

### Claim 26 (depends on 25)

The method of claim 25, wherein the annealing process is performed in an H2 atmosphere.

### Claim 27 (depends on 25)

The method of claim 25, wherein the annealing process is performed at a temperature of about 850-950° C.

### Claim 28 (depends on 25)

The method of claim 25, wherein the semiconductor body includes five planes or seven planes facing different directions.

### Claim 29 (depends on 28)

The method of claim 28, wherein the semiconductor body, which contains channels formed on five planes, includes a first surface perpendicular to the main surface of the substrate, a second surface parallel to the main surface of the substrate, and a third surface including a {111} crystal plane or a {311} crystal plane.

### Claim 30 (depends on 28)

The method of claim 28, wherein the semiconductor body, which contains channels formed on seven planes, includes a first surface perpendicular to the main surface of the substrate, a second surface parallel to the main surface of the substrate, a third surface including a {111} crystal plane, and a fourth surface including a {311} crystal plane.

### Claim 31 (depends on 25)

The method of claim 25, further comprising:
etching a portion of the substrate to form a trench for defining the semiconductor fin; and
filling the trench with an insulating material to form a device isolation region around the semiconductor fin.

### Claim 32 (depends on 25)

The method of claim 25, further comprising forming a blocking insulating layer covering a portion of an upper surface of the semiconductor fin before forming the semiconductor body.

### Claim 33 (depends on 24)

The method of claim 24, wherein the semiconductor body is formed over an oxide layer fin formed on the substrate, the floating gate is formed on the semiconductor body and a sidewall of the oxide layer fin, and the control gate is formed along the intergate insulating layer and an upper portion of the substrate.

### Claim 34 (depends on 33)

The method of claim 33, wherein the forming of the semiconductor body comprises:
undercutting a lower portion of the semiconductor body, which contains channels formed on three planes;
rounding the edges of an upper portion of the undercut semiconductor body; and
annealing the rounded semiconductor body.

### Claim 35 (depends on 34)

The method of claim 34, further comprising forming an oxide layer on a sidewall of the undercut semiconductor body and an undercut region before rounding the edges of the upper portion of the semiconductor body.

### Claim 36 (depends on 34)

The method of claim 34, wherein the edges of the upper portion of the semiconductor body are rounded by at least one process selected from dry etching, wet etching and annealing.

### Claim 37 (depends on 35)

The method of claim 35, wherein the substrate is a silicon-on-insulator (SOI) substrate having a buried oxide film, and the oxide layer fin is formed by wet etching the buried oxide film of the SOI substrate.

### Claim 38

A nonvolatile semiconductor device comprising:
a semiconductor body elongated in one direction on a substrate, and having a cross section perpendicular to a main surface of the substrate and to the elongated direction, the cross section having a predetermined curvature;
a channel region partially formed on the semiconductor body along the circumference of the semiconductor body;
a tunneling insulation disposed on the channel region;
a floating gate disposed on the tunneling insulating layer, and electrically insulated from the channel region;
a high dielectric constant material layer disposed on the floating gate;
a metallic control gate disposed on the material having the high dielectric constant and electrically insulated from the floating gate; and
source and drain regions that are adjacent to sides of the control gate and formed on the semiconductor body.

### Claim 39 (depends on 38)

The nonvolatile semiconductor device of claim 38, wherein the cross section of the semiconductor body is shaped in one of a semi-circle, a circle, or an oval.

### Claim 40 (depends on 38)

The nonvolatile semiconductor device of claim 38, wherein the substrate is a bulk substrate or a silicon-on-insulator (SOI) substrate.

### Claim 41 (depends on 38)

The nonvolatile semiconductor device of claim 38, wherein the floating gate is a nitride layer (Si3N4).

### Claim 42 (depends on 38)

The nonvolatile semiconductor device of claim 38, wherein the high dielectric constant material layer is a combination of hafnium oxide (HfO2), zirconium oxide (ZrO4), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), hafnium silicate (HfSiO), and zirconium silicate (O4SiZr).

### Claim 43 (depends on 38)

The nonvolatile semiconductor device of claim 38, wherein the metallic control gate is made of a metal, metal nitride, metal silicide, or a combination thereof.