# US 7,411,238 B2 · Semiconductor integrated circuit device and a method of manufacturing the same

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- Number: US 7,411,238 B2
- Document ID: US7411238B2
- Status: Granted
- Kind: B2
- Application number: 11/584,623
- Filed: 2006-10-23
- Published: 2007-02-15
- Granted: 2008-08-12
- Earliest claimed: 2003-02-21
- Assignees: Renesas Technology Corp.
- Inventors: Akio Nishida; Hiraku Chakihara; Koichi Toba
- Web page: https://patentgrep.com/patent/US7411238B2

## CPC

- G11C 11/4125: {Cells incorporating circuit means for protecting against loss of information}
- H10B 10/00: Static random access memory [SRAM] devices
- H10B 10/12: {comprising a MOSFET load element}
- H10B 10/18: {Peripheral circuit regions}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

In order to improve the soft error resistance of a memory cell of an SRAM without increasing its chip size in deep through-holes formed by perforating a silicon oxide film, there is a silicon nitride film and a silicon oxide film, a capacitor element having a TIN film serving as a lower electrode. This capacitor element is connected between a storage node and a supply voltage line, between a storage node and a reference voltage line, or between storage nodes of the memory cell of the SRAM.

## Claims

### Claim 1

A semiconductor integrated circuit device comprising:
a memory cell having a first and a second drive MISFET and a first and a second load MISFET,
the first and the second drive MISFET each having a source region and a drain region formed in a substrate,
the first and the second load MISFET each having a source region and a drain region formed in a substrate,
gate electrodes of the first and second drive MISFET and the first and second load MISFET formed over a main surface of the substrate;
a first insulating film is formed over the first and second drive MISFET and the first and second load MISFET,
wherein the first insulating film has a first opening and a second opening;
a first capacitor element formed over the side wall and bottom of the first opening such that the first capacitor element has, as a lower electrode, a first conductive film formed along the side wall and bottom of the first opening, as a capacitor insulator film, a second insulating film formed over the first conductive film, and as an upper electrode, a second conductive film formed over the second insulating film; and
a second capacitor element formed over the side wall and bottom of the second opening such that the second capacitor element has, as a lower electrode, a third conductive film formed along the side wall and bottom of the second opening, as a capacitor insulator film, a third insulating film formed over the third conductive film, and as an upper electrode, a fourth conductive film formed over the third insulating film,
wherein the first opening is formed to extend over the drain region of the first drive MISFET and the drain region of the first load MISFET such that the first conductive film is electrically connected to the drain of the first drive MISFET, the drain of the first load MISFET, the gate electrode of the second drive MISFET and the gate electrode of the second load MISFET,
wherein the second opening is formed to extend over the drain region of the second drive MISFET and the drain region of the second load MISFET such that the third conductive film is electrically connected to the drain of the second drive MISFET, the drain of the second load MISFET, the gate electrode of the first drive MISFET and the gate electrode of the first load MISFET.

### Claim 2 (depends on 1)

A semiconductor integrated circuit device according to claim 1, wherein the first opening reaches the drain region of the first drive MISFET and the drain region of the first load MISFET, wherein the second opening reaches the drain region of the second drive MISFET and the drain region of the second load MISFET.

### Claim 3 (depends on 1)

A semiconductor integrated circuit device according to claim 1, wherein the second conductive film is electrically connected to the fourth conductive film.

### Claim 4 (depends on 1)

A semiconductor integrated circuit device according to claim 1, wherein the second conductive film is integrally formed with the fourth conductive film.

### Claim 5 (depends on 1)

A semiconductor integrated circuit device according to claim 1, wherein a fixed potential (Vcc, Vss) is applied to the second conductive film and the fourth conductive film.

### Claim 6

A semiconductor integrated circuit device comprising:
a memory cell having a first and a second drive MISFET and a first and a second load MISFET,
the first and the second drive MISFET each having a source region and a drain region formed in a substrate,
the first and the second load MISFET each having a source region and a drain region formed in a substrate,
gate electrodes of the first and second drive MISFET and the first and second load MISFET formed over a main surface of the substrate;
a first insulating film is formed over the first and second drive MISFET and the first and second load MISFET,
wherein the first insulating film has a first opening and a second opening;
a first capacitor element formed over the side wall and bottom of the first opening such that the first capacitor element has, as a lower electrode, a first conductive film formed along the side wall and bottom of the first opening, as a capacitor insulator film, a second insulating film formed over the first conductive film, and as an upper electrode, a second conductive film formed over the second insulating film; and
a second capacitor element formed over the side wall and bottom of the second opening such that the second capacitor element has, as a lower electrode, a third conductive film formed along the side wall and bottom of the second opening, as a capacitor insulator film, a third insulating film formed over the third conductive film, and as an upper electrode, a fourth conductive film formed over the third insulating film,
wherein the first conductive film is electrically connected to the drain of the first drive MISFET, the drain of the first load MISFET, the gate electrode of the second drive MISFET and the gate electrode of the second load MISFET,
wherein the third conductive film is electrically connected to the drain of the second drive MISFET, the drain of the second load MISFET, the gate electrode of the first drive MISFET and the gate electrode of the first load MISFET.

### Claim 7 (depends on 6)

A semiconductor integrated circuit device according to claim 6, wherein the first opening reaches the drain region of the first drive MISFET and the drain region of the first load MISFET, wherein the second opening reaches the drain region of the second drive MISFET and the drain region of the second load MISFET.

### Claim 8 (depends on 6)

A semiconductor integrated circuit device according to claim 6, wherein the second conductive film is electrically connected to the fourth conductive film.

### Claim 9 (depends on 6)

A semiconductor integrated circuit device according to claim 6, wherein the second conductive film is integrally formed with the fourth conductive film.

### Claim 10 (depends on 6)

A semiconductor integrated circuit device according to claim 6, wherein a fixed potential is applied to the second conductive film and the fourth conductive film.