# US 7,411,237 B2 · Lanthanum hafnium oxide dielectrics

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- Number: US 7,411,237 B2
- Document ID: US7411237B2
- Status: Granted
- Kind: B2
- Application number: 11/584,229
- Filed: 2006-10-20
- Published: 2007-02-15
- Granted: 2008-08-12
- Earliest claimed: 2004-12-13
- Assignees: Micron Technology, Inc.
- Inventors: Kie Y. Ahn; Leonard Forbes
- Web page: https://patentgrep.com/patent/US7411237B2

## CPC

- H10P 14/69392: {the material containing hafnium, e.g. HfO2}
- C23C 16/40: Oxides
- C23C 16/45531: {specially adapted for making ternary or higher compositions}
- C23C 16/45553: {characterized by the use of precursors specially adapted for ALD}
- H10P 14/662: {Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548)}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/69396: {the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium}
- H10P 14/69397: {the material containing two or more metal elements}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)

## Abstract

Dielectric layers containing a lanthanum hafnium oxide layer, where the lanthanum hafnium oxide layer is arranged as a structure of one or more monolayers, provide an insulating layer in a variety of structures for use in a wide range of electronic devices.

## Claims

### Claim 1

An electronic device comprising:
a substrate having an integrated circuit; and
a dielectric layer disposed on the substrate as part of the integrated circuit, the dielectric layer containing a lanthanum hafnium oxide layer and a lanthanide other than lanthanum, the lanthanum hafnium oxide layer structured as one or more monolayers of lanthanum hafnium oxide.

### Claim 2 (depends on 1)

The electronic device of claim 1, wherein the dielectric layer includes a dielectric stack having the lanthanum hafnium oxide layer on a silicon oxide layer.

### Claim 3 (depends on 1)

The electronic device of claim 1, wherein the lanthanum hafnium oxide layer includes a substantial amount of La2Hf2O7.

### Claim 4 (depends on 1)

The electronic device of claim 1, wherein the lanthanum hafnium oxide layer is essentially a layer of La2Hf2O7.

### Claim 5 (depends on 1)

The electronic device of claim 1, wherein the lanthanum hafnium oxide layer is doped with the lanthanide other than lanthanum.

### Claim 6 (depends on 1)

The electronic device of claim 1, wherein the dielectric layer includes a layer of an insulating metal oxide in addition to the lanthanum hafnium oxide layer.

### Claim 7 (depends on 1)

The electronic device of claim 1, wherein the dielectric layer is structured as a nanolaminate.

### Claim 8 (depends on 1)

The electronic device of claim 1, wherein the dielectric layer is structured as a capacitor dielectric in a capacitor.

### Claim 9 (depends on 1)

The electronic device of claim 1, wherein the dielectric layer is structured as a gate insulator in a silicon complementary metal-oxide-semiconductor field effect (CMOS) transistor.

### Claim 10 (depends on 1)

The electronic device of claim 1, wherein the dielectric layer is structured as a gate insulator on and contacting a channel region, the channel region being between a source region and a drain region of a transistor.

### Claim 11 (depends on 1)

The electronic device of claim 1, wherein the dielectric layer is structured as a floating gate dielectric of a transistor, the floating gate dielectric disposed between and in contact with a floating gate and a control gate.

### Claim 12 (depends on 1)

The electronic device of claim 1, wherein the integrated circuit includes an analog integrated circuit.

### Claim 13 (depends on 1)

The electronic device of claim 1, wherein the integrated circuit includes a radio frequency integrated circuit.

### Claim 14 (depends on 1)

The electronic device of claim 1, wherein the integrated circuit includes a mixed signal integrated circuit.

### Claim 15 (depends on 1)

The electronic device of claim 1, wherein the electron device includes a memory.

### Claim 16

A memory including:
an array of memory cells on a substrate, a memory cell having a semiconductor device; and
a dielectric layer disposed in the semiconductor device, the dielectric layer containing a lanthanum hafnium oxide layer and a lanthanide other than lanthanum, the lanthanum hafnium oxide layer structured as one or more monolayers of lanthanum hafnium oxide.

### Claim 17 (depends on 16)

The memory of claim 16, wherein the dielectric layer is a gate insulator of a transistor in the memory cell.

### Claim 18 (depends on 16)

The memory of claim 16, wherein the memory includes a flash memory device.

### Claim 19 (depends on 18)

The memory of claim 18, wherein the dielectric layer is an inter-gate insulator between and contacting a floating gate and a control gate of a transistor in the flash memory device.

### Claim 20 (depends on 18)

The memory of claim 18, wherein the dielectric layer is a gate insulator between and contacting a floating gate and a channel of a transistor in the flash memory device.

### Claim 21 (depends on 16)

The memory of claim 16, wherein the dielectric layer is a dielectric of a capacitor in the memory cell.

### Claim 22 (depends on 16)

The memory of claim 16, wherein the dielectric layer is a nanolaminate in a NROM flash memory device.

### Claim 23 (depends on 16)

The memory of claim 16, wherein the dielectric layer includes a dielectric stack having the lanthanum hafnium oxide layer on a silicon oxide layer.

### Claim 24 (depends on 16)

The memory of claim 16, wherein the lanthanum hafnium oxide layer includes a substantial amount of La2Hf2O7.

### Claim 25

A system comprising:
a controller; and
an integrated circuit coupled to the controller, wherein at least one of the controller or integrated circuit includes a dielectric layer disposed on a substrate, the dielectric layer containing a lanthanum hafnium oxide layer and a lanthanide other than lanthanum, the lanthanum hafnium oxide layer structured as one or more monolayers of lanthanum hafnium oxide.

### Claim 26 (depends on 25)

The system of claim 25, wherein the dielectric layer includes a dielectric stack having the lanthanum hafnium oxide layer on a silicon oxide layer.

### Claim 27 (depends on 25)

The system of claim 25, wherein the lanthanum hafnium oxide layer includes a substantial amount of La2Hf2O7.

### Claim 28 (depends on 25)

The system of claim 25, wherein the lanthanum hafnium oxide layer is doped with the lanthanide other than lanthanum.

### Claim 29 (depends on 25)

The system of claim 25, wherein the integrated circuit includes a memory.

### Claim 30 (depends on 25)

The system of claim 25, wherein the dielectric layer is an inter-gate insulator between and contacting a floating gate and a control gate of a transistor.

### Claim 31 (depends on 25)

The system of claim 25, wherein the dielectric layer is a gate insulator between and contacting a gate and a channel of a transistor.

### Claim 32 (depends on 25)

The system of claim 25, wherein the controller includes a processor.

### Claim 33 (depends on 25)

The system of claim 25, wherein the integrated circuit includes a mixed signal integrated circuit.

### Claim 34 (depends on 25)

The system of claim 25, wherein the system is an information handling system.

### Claim 35 (depends on 25)

The system of claim 25, wherein the system is a wireless system.