# US 7,411,217 B2 · Thin film transistor array substrate and manufacturing method of the same

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- Number: US 7,411,217 B2
- Document ID: US7411217B2
- Status: Granted
- Kind: B2
- Application number: 11/594,950
- Filed: 2006-11-09
- Published: 2007-03-08
- Granted: 2008-08-12
- Earliest claimed: 2002-12-31
- Assignees: LG Display Co., Ltd.
- Inventors: Soon Sung Yoo; Youn Gyoung Chang; Heung Lyul Cho
- Web page: https://patentgrep.com/patent/US7411217B2

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- G02F 1/13458: {Terminal pads}
- G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/40: characterised by multiple TFTs
- H10D 86/441: {Interconnections, e.g. scanning lines}
- G02F 1/136213: {Storage capacitors associated with the pixel electrode}
- G02F 1/136236: {using a grey or half tone lithographic process}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- Y10S 438/942: Masking
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A thin film transistor array substrate has a gate electrode of the thin film transistor, a gate line connected to the gate electrode, and a gate pad connected to the gate line; a source/drain pattern including a source electrode and a drain electrode of the thin film transistor, a data line connected to the source electrode, a data pad connected to the data line, a storage electrode formed and superimposed with the gate line; a semiconductor pattern formed in low part of the substrate; a transparent electrode pattern including a pixel electrode connected to the drain electrode and the storage electrode, a gate pad protection electrode covering the gate pad, and a data pad protection electrode covering the data pad; and a protection pattern and a gate insulation pattern stacked in a region other than the region where the transparent electrode pattern is formed.

## Claims

### Claim 1

A thin film transistor array substrate, comprising:
a gate pattern including:
a gate electrode of the thin film transistor;
a gate line to which the gate electrode is connected; and
a gate pad to which the gate line is connected;
a source/drain pattern including:
a source electrode and a drain electrode of the thin film transistor;
a data line connected to the source electrode;
a data pad connected to the data line;
a storage electrode formed and superimposed with the gate line;
a semiconductor pattern formed in a low region of the substrate corresponding to the source/drain pattern;
a transparent electrode including a pixel electrode connected to the drain electrode and the storage electrode, a gate pad protection electrode covering the gate pad, and a data pad protection electrode formed to cover the data pad; and
a protection pattern and a gate insulation pattern stacked in the remainder region except for the region where the transparent electrode pattern is formed.

### Claim 2 (depends on 1)

The thin film transistor array substrate according to claim 1, wherein the protection pattern partially exposes the drain electrode and the storage electrode and is connected to the pixel electrode.

### Claim 3

A thin film transistor array substrate, comprising:
a gate electrode of the thin film transistor;
a gate line to which the gate electrode is connected; and
a gate pad to which the gate line is connected;
a source electrode and a drain electrode of the thin film transistor;
a data line connected to the source electrode;
a data pad connected to the data line;
a storage electrode formed and superimposed over the gate line;
a transparent electrode including a pixel electrode connected to the drain electrode and the storage electrode, a gate pad protection electrode covering the gate pad, and a data pad protection electrode formed to cover the data pad; and
a protection layer and a gate insulation layer stacked in a region of the substrate other than the region where the transparent electrode is formed.

### Claim 4 (depends on 3)

The thin film transistor array substrate according to claim 3, wherein the protection layer partially exposes the drain electrode and the storage electrode and is connected to the pixel electrode.