# US 7,410,875 B2 · Semiconductor structure and fabrication thereof

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- Number: US 7,410,875 B2
- Document ID: US7410875B2
- Status: Granted
- Kind: B2
- Application number: 11/400,077
- Filed: 2006-04-06
- Published: 2007-10-11
- Granted: 2008-08-12
- Earliest claimed: 2006-04-06
- Assignees: United Microelectronics Corp.
- Inventors: Shyh-Fann Ting; Cheng-Tung Huang; Wen-Han Hung; Li-Shian Jeng; Tzyy-Ming Cheng
- Web page: https://patentgrep.com/patent/US7410875B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for fabricating a semiconductor structure is described. A substrate is provided, having thereon a gate structure and a spacer on the sidewall of the gate structure and having therein an S/D extension region beside the gate structure. An opening is formed in the substrate beside the spacer, and then an S/D region is formed in or on the substrate at the bottom of the opening. A metal silicide layer is formed on the S/D region and the gate structure, and then a stress layer is formed over the substrate.

## Claims

### Claim 1

A method for fabricating a semiconductor structure, comprising:
providing a substrate having thereon a gate structure and a spacer on a sidewall of the gate structure and having therein an S/D extension region beside the gate structure;
forming an opening in the substrate beside the spacer;
forming an S/D region in or on the substrate at bottom of the opening;
forming a metal silicide layer on the S/D region and the gate structure; and
forming a stress layer over the substrate and filling the opening, wherein the stress layer has a sufficient thickness to at least fill up the opening.

### Claim 2 (depends on 1)

The method of claim 1, wherein the step of forming the opening comprises:
forming over the substrate a patterned photoresist layer exposing the substrate beside the spacer;
etching and removing a portion of the exposed substrate using the patterned photoresist layer and the spacer as a mask; and
removing the patterned photoresist layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the etching comprises isotropic etching, anisotropic etching or tapered etching.

### Claim 4 (depends on 1)

The method of claim 1, wherein the step of forming the metal isotropic etching, anisotropic etching or tapered etching.

### Claim 5 (depends on 1)

The method of claim 1, wherein the step of forming the S/D region comprises an ion implantation process using the spacer and the gate structure as a mask.

### Claim 6 (depends on 1)

The method of claim 1, wherein the step of forming the S/D region comprises a selective epitaxy growth (SEG) process with in-situ doping.

### Claim 7 (depends on 1)

The method of claim 1, wherein the stress layer is a compressive stress layer or a tensile stress layer.

### Claim 8 (depends on 1)

The method of claim 1, wherein the opening has a depth of about 100-1000 Å.

### Claim 9

A method for fabricating a semiconductor structure, comprising:
providing a substrate having a first and a second gate structures thereon;
forming a first S/D extension region of a first conductivity type in the substrate beside the first gate structure, and forming a second S/D extension region of a second conductivity type in the substrate beside the second gate structure;
forming a first spacer on a sidewall of the first gate structure, and forming a second spacer on a sidewall of the second gate structure;
forming an opening in the substrate beside the first spacer;
forming a first S/D region of the first conductivity type in or on the substrate at bottom of the opening to form a first MOS transistor of the first conductivity type, and forming a second S/D region of the second conductivity type in the substrate beside the second spacer to form a second MOS transistor of the second conductivity type; and
forming a first stress layer over the first MOS transistor and filling the opening, and forming a second stress layer over the second MOS transistor, wherein the first stress layer has a sufficient thickness to at least fill up the opening.

### Claim 10 (depends on 9)

The method of claim 9, further comprising forming a metal silicide layer on the first and the second S/D regions and the first and the second gate structures.

### Claim 11 (depends on 10)

The method of claim 10, wherein the step of forming the metal silicide layer comprises a salicide process.

### Claim 12 (depends on 9)

The method of claim 9, wherein the step of forming the opening comprises:
forming over the substrate a patterned photoresist layer exposing the substrate beside the first spacer;
etching and removing a portion of the exposed substrate using the patterned photoresist layer and the first spacer as a mask; and
removing the patterned photoresist layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein the etching comprises isotropic etching, anisotropic etching or tapered etching.

### Claim 14 (depends on 9)

The method of claim 9, wherein the step of forming the first S/D region comprises an ion implantation process of the first conductivity type using the first spacer and the first gate structure as a mask.

### Claim 15 (depends on 9)

The method of claim 9, wherein the step of forming the first S/D region comprises a selective epitaxy growth (SEG) process with in-situ doping.

### Claim 16 (depends on 9)

The method of claim 9, wherein the step of forming the second S/D region comprises an ion implantation process of the second conductivity type using the second spacer and the second gate structure as a mask.

### Claim 17 (depends on 9)

The method of claim 9, wherein the step of forming the first S/D extension region comprises an ion implantation process of the first conductivity type using the first gate structure as a mask.

### Claim 18 (depends on 9)

The method of claim 9, wherein the step of forming the second S/D extension region comprises an ion implantation process of the second conductivity type using the second gate structure as a mask.

### Claim 19 (depends on 9)

The method of claim 9, wherein the opening has a depth of about 100-1000 Å.

### Claim 20 (depends on 9)

The method of claim 9, wherein the first conductivity type is P-type, the second conductivity type is N-type, the first stress layer is a compressive stress layer, and the second stress layer is a tensile stress layer.

### Claim 21 (depends on 9)

The method of claim 9, wherein the first conductivity type is N-type and the second conductivity type is P-type, the first stress layer is a tensile stress layer, and the second stress layer is a compressive stress layer.