# US 7,410,872 B2 · Sealing method for electronic devices formed on a common semiconductor substrate and corresponding circuit structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,410,872 B2 - Document ID: US7410872B2 - Status: Granted - Kind: B2 - Application number: 11/457,966 - Filed: 2006-07-17 - Published: 2007-02-01 - Granted: 2008-08-12 - Earliest claimed: 2003-10-22 - Assignees: STMicroelectronics S.r.l. - Inventors: Alfonso Maurelli - Web page: https://patentgrep.com/patent/US7410872B2 ## CPC - H10B 41/40: characterised by the peripheral circuit region - H10B 41/44: with a control gate layer also being used as part of the peripheral transistor - H10D 84/0147: {Manufacturing their gate sidewall spacers} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10W 74/147: {the encapsulations being multilayered} - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method for sealing electronic devices formed on a semiconductor substrate includes forming a plurality of first electronic devices adjacent a first portion of the semiconductor substrate, with each first electronic device including a first region comprising at least one first conductive layer projecting from the semiconductor substrate. A first sealing layer is formed adjacent the first regions for sealing the plurality of first electronic devices. A protective layer is formed adjacent the first sealing layer. The protective layer is etched to form protective spacers adjacent sidewalls of the first regions. The method further includes forming a plurality of second electronic devices adjacent a second portion of the semiconductor substrate, with each second electronic device including a second region comprising a second conductive layer projecting from the semiconductor substrate. A second sealing layer is formed adjacent the second regions for sealing the plurality of second electronic devices, and adjacent the first sealing layer for sealing the plurality of first electronic devices. ## Claims ### Claim 1 A method for sealing electronic devices formed on a semiconductor substrate comprising: forming a plurality of first electronic devices adjacent a first portion of the semiconductor substrate, each first electronic device including a first region comprising at least one first conductive layer projecting from the semiconductor substrate; forming a first sealing layer on the first regions including sidewalls thereof for sealing the plurality of first electronic devices; forming a protective layer on the first sealing layer; etching the protective layer to form protective spacers on the first sealing layer for the first regions; forming a plurality of second electronic devices adjacent a second portion of the semiconductor substrate, each second electronic device including a second region comprising a second conductive layer projecting from the semiconductor substrate; and forming a second sealing layer on the second regions including sidewalls thereof for sealing the plurality of second electronic devices, and on the first sealing layer for sealing the plurality of first electronic devices; said second sealing layer covering top portions of said second regions of said plurality of second electronic devices, with said first sealing layer between the top portions and said second sealing layer. ### Claim 2 (depends on 1) A method according to claim 1, wherein the protective layer is selectively etched with respect to the first sealing layer. ### Claim 3 (depends on 1) A method according to claim 1, wherein the protective layer comprises a silicon nitride layer. ### Claim 4 (depends on 1) A method according to claim 1, wherein the first sealing layer is formed adjacent the second conductive layer. ### Claim 5 (depends on 1) A method according to claim 1, wherein a thickness of the second sealing layer is different from a thickness of the first sealing layer. ### Claim 6 (depends on 5) A method according to claim 5, wherein the thickness of the second sealing layer is less than the thickness of the first sealing layer. ### Claim 7 (depends on 1) A method according to claim 1, wherein a thickness of the second sealing layer is within a range of about 1 to 4 nm, and a thickness of the first sealing layer is within a range of about 3 to 15 nm. ### Claim 8 (depends on 1) A method according to claim 1, wherein forming the at least one first conductive layer comprises forming a lower conductive layer, a dielectric layer adjacent the lower conductive layer, and an upper conductive layer adjacent the dielectric layer. ### Claim 9 (depends on 8) A method according to claim 8, wherein the upper conductive layer is formed when the second conductive layer is formed. ### Claim 10 (depends on 1) A method according to claim 1, wherein the first sealing layer is formed adjacent the semiconductor substrate between the plurality of first electronic devices; and further comprising forming a first insulating layer between the first sealing layer and the semiconductor substrate, and between the plurality of first electronic devices and the semiconductor substrate. ### Claim 11 (depends on 1) A method according to claim 1, wherein the second sealing layer is formed adjacent the semiconductor substrate between the plurality of second electronic devices; and wherein a second insulating layer is formed between the second sealing layer and the semiconductor substrate, and between the plurality of second electronic devices and the semiconductor substrate. ### Claim 12 A method for making an integrated circuit comprising: forming at least one first conductive layer adjacent a first portion of a semiconductor substrate; forming a second conductive layer adjacent a second portion of the semiconductor substrate; forming a plurality of memory cells in the at least one first conductive layer and the first portion of the semiconductor substrate; forming a first sealing layer on the plurality of memory cells including sidewalls thereof; forming protective spacers on the first sealing layer for the plurality of memory cells, each protective spacer comprising a protective layer; forming a plurality of transistors in the second conductive layer; and forming a second sealing layer on the plurality of transistors including sidewalls thereof, and directly on the first sealing layer. ### Claim 13 (depends on 12) A method according to claim 12, wherein each protective layer comprises a silicon nitride layer. ### Claim 14 (depends on 12) A method according to claim 12, wherein the first sealing layer is formed on the second conductive layer. ### Claim 15 (depends on 12) A method according to claim 12, wherein the thickness of the second sealing layer is less than the thickness of the first sealing layer. ### Claim 16 (depends on 12) A method according to claim 12, wherein a thickness of the second sealing layer is within a range of about 1 to 4 nm, and a thickness of the first sealing layer is within a range of about 3 to 15 nm. ### Claim 17 (depends on 12) A method according to claim 12, wherein the first sealing layer is formed adjacent the semiconductor substrate between the plurality of memory cells; and wherein a first insulating layer is formed between the first sealing layer and the semiconductor substrate, and between the plurality of memory cells and the semiconductor substrate. ### Claim 18 (depends on 12) A method according to claim 12, wherein the first sealing layer is also formed between top portions of the plurality of transistors and the second sealing layer. ### Claim 19 (depends on 12) A method according to claim 12, wherein the second sealing layer is formed adjacent the semiconductor substrate between the plurality of transistors; and wherein a second insulating layer is formed between the second sealing layer and the semiconductor substrate, and between the plurality of transistors and the semiconductor substrate. ### Claim 20 (depends on 12) A method according to claim 12, further comprising removing a portion of the first sealing layer and a portion of the second sealing layer for exposing an upper surface of the at least one conductive layer. ### Claim 21 An integrated circuit comprising: a semiconductor substrate including first and second portions; a plurality of first electronic devices adjacent the first portion of said semiconductor substrate, each first electronic device including a first region comprising at least one first conductive layer projecting from said semiconductor substrate; a first sealing layer on said plurality of first electronic devices including sidewalls thereof; protective spacers on said first sealing layer for said plurality of first electronic devices, each protective spacer comprising a protective layer; a plurality of second electronic devices adjacent the second portion of said semiconductor substrate, each second electronic device including a second region comprising a second conductive layer projecting from said semiconductor substrate; and a second sealing layer on said plurality of second electronic devices including sidewalls thereof, and on portions of said first sealing layer and on said protective spacers for said plurality of first electronic devices, said second sealing layer covering top portions of said second regions of said plurality of second electronic devices, with said first sealing layer between the top portions and said second sealing layer. ### Claim 22 (depends on 21) An integrated circuit according to claim 21, wherein each protective layer comprises a silicon nitride layer. ### Claim 23 (depends on 21) An integrated circuit according to claim 21, wherein a thickness of said second sealing layer is less than a thickness of said first sealing layer. ### Claim 24 (depends on 21) An integrated circuit according to claim 21, wherein said second sealing layer is directly on said first sealing layer. ### Claim 25 (depends on 21) An integrated circuit according to claim 21, wherein said first sealing layer is adjacent said semiconductor substrate between said plurality of first electronic devices; and further comprising a first insulating layer between said semiconductor substrate and said first regions, and adjacent said semiconductor substrate between said plurality of first electronic devices. ### Claim 26 (depends on 25) An integrated circuit according to claim 25, wherein said first sealing layer is adjacent said first insulating layer between said plurality of first electronic devices. ### Claim 27 (depends on 21) An integrated circuit according to claim 21, wherein said plurality of first electronic devices comprises a plurality of now-volatile memory cells, and wherein said at least one conductive layer projecting from said semiconductor substrate forms gate regions for said plurality of non-volatile memory cells; and wherein said plurality of second electronic devices comprises a plurality of transistors, and wherein said conductive layer projecting from said semiconductor substrate forms gate regions for said plurality of transistors. ### Claim 28 (depends on 21) An integrated circuit according to claim 21, wherein a thickness of said first sealing layer is within a range of about 3 to 15 nm; and wherein a thickness of said second sealing layer is within a range of about 1 to 4 nm. ### Claim 29 An integrated circuit comprising: a semiconductor substrate including first and second portions; a plurality of memory cells adjacent the first portion of said semiconductor substrate; a first sealing layer on said plurality of memory cells including sidewalls thereof; protective spacers on said first sealing layer for the plurality of memory cells, each protective spacer comprising a protective layer; a plurality of transistors adjacent the second portion of said semiconductor substrate; and a second sealing layer on said plurality of transistors including sidewalls thereof and directly on said first sealing layer. ### Claim 30 (depends on 29) An integrated circuit according to claim 29, wherein each protective layer comprises a silicon nitride layer. ### Claim 31 (depends on 29) An integrated circuit according to claim 29, wherein a thickness of said second sealing layer is different from a thickness of said first sealing layer. ### Claim 32 (depends on 29) An integrated circuit according to claim 29, wherein said first sealing layer is also between said plurality of second electronic devices and said second sealing layer; and wherein said second sealing layer is adjacent sidewalls of said plurality of transistors. ### Claim 33 (depends on 29) An integrated circuit according to claim 29, wherein a thickness of said first sealing layer is within a range of about 3 to 15 nm; and wherein a thickness of said second sealing layer is within a range of about 1 to 4 nm. ### Claim 34 An integrated circuit comprising: a semiconductor substrate including first and second portions; a plurality of first electronic devices adjacent the first portion of said semiconductor substrate, each first electronic device including a first region comprising at least one first conductive layer projecting from said semiconductor substrate; first spacers on sidewalls of the first regions of said plurality of first electronic devices, said first spacers defined by a first sealing layer, a protective layer on said first sealing layer and a second sealing layer on said protective layer; a plurality of second electronic devices adjacent the second portion of said semiconductor substrate, each second electronic device including a second region comprising a second conductive layer projecting from said semiconductor substrate; and second spacers on sidewalls of the second regions of said plurality of second electronic devices, said second spacers defined by other portions of the second sealing layer, said second sealing layer covering top portions of said second regions of said plurality of second electronic devices, with said first sealing layer between the top portions and said second sealing layer. ### Claim 35 (depends on 34) An integrated circuit according to claim 34, wherein said protective layer comprises a silicon nitride layer. ### Claim 36 (depends on 34) An integrated circuit according to claim 34, wherein a thickness of said second sealing layer is less than a thickness of said first sealing layer. ### Claim 37 (depends on 34) An integrated circuit according to claim 34, wherein said second sealing layer is directly on said first sealing layer; and wherein said second sealing sayer is directly on sidewalls of said second regions. ### Claim 38 (depends on 34) An integrated circuit according to claim 34, wherein said first sealing layer is adjacent said semiconductor substrate between said plurality of first electronic devices. ### Claim 39 (depends on 34) An integrated circuit according to claim 34, wherein said plurality of first electronic devices comprise a plurality of nonvolatile memory cells; and wherein the at least one first conductive layer projecting from said semiconductor substrate forms gate regions for said plurality of nonvolatile memory cells; and wherein said plurality of second electronic devices comprise a plurality of transistors; and wherein the second conductive layer projecting from said semiconductor substrate forms gate regions for said plurality of transistors. ### Claim 40 (depends on 34) An integrated circuit according to claim 34, wherein a thickness of said first sealing layer is within a range of about 3 to 15 nm; and wherein a thickness of said second sealing layer is within a range of about 1 to 4 nm. ### Claim 41 (depends on 34) An integrated circuit according to claim 34, further comprising an insulating layer between said semiconductor substrate and the first regions, and between said semiconductor substrate and said first sealing layer.