# US 7,410,869 B2 · Method of manufacturing a semiconductor device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,410,869 B2
- Document ID: US7410869B2
- Status: Granted
- Kind: B2
- Application number: 11/480,380
- Filed: 2006-07-05
- Published: 2007-02-01
- Granted: 2008-08-12
- Earliest claimed: 2005-07-05
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Hun-Hyeoung Leam; Hyeon-Deok Lee; Young-Sub You; Won-Jun Jang; Woong Lee; Jung-Hyun Park; Sang-Kyoung Lee; Jung-Geun Jee; Sang-Hoon Lee
- Web page: https://patentgrep.com/patent/US7410869B2

## CPC

- H10B 41/30: characterised by the memory core region
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10P 95/04: {Planarisation of conductive or resistive materials}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

In a method of manufacturing a semiconductor device such as a flash memory device, an insulating pattern having an opening is formed to partially expose a surface of a substrate. A first silicon layer is formed on the exposed surface portion of the substrate and the insulating pattern. The first silicon layer has an opened seam overlying the previously exposed portion of the substrate. A heat treatment on the substrate is performed at a temperature sufficient to induce silicon migration so as to cause the opened seam to be closed via the silicon migration. A second silicon layer is then formed on the first silicon layer. Thus, surface profile of a floating gate electrode obtained from the first and second silicon layers may be improved.

## Claims

### Claim 1

A method of manufacturing an inchoate semiconductor device, the method comprising:
forming an insulating pattern having an opening partially exposing a surface of a substrate;
forming a first silicon layer, on the insulating pattern and the exposed surface portion of the substrate, having an opened seam overlying the previously exposed portion of the substrate;
forming a silicon oxide layer on the first silicon layer;
heat treating the first silicon layer at a temperature sufficient to induce silicon migration so as to cause the opened seam to be closed, wherein the first silicon layer is heat treated under an atmosphere including hydrogen, and the silicon migration is promoted by a reduction reaction between hydrogen and the silicon oxide layer; and
forming a second silicon layer on the first silicon layer after having closed the opened seam.

### Claim 2 (depends on 1)

The method of claim 1, wherein the silicon oxide layer is formed by exposing the first silicon layer to an atmosphere including oxygen.

### Claim 3 (depends on 1)

The method of claim 1, wherein the heat treatment is performed at a temperature of about 850 to about 1000°C.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first silicon layer includes impurity doped amorphous silicon and is crystallized by the heat treatment.

### Claim 5 (depends on 1)

The method of claim 1, wherein the second silicon layer includes impurity doped polysilicon.

### Claim 6 (depends on 1)

The method of claim 1, further comprising
forming a tunnel insulating layer on the exposed surface portion of the substrate after forming the insulating pattern.

### Claim 7 (depends on 1)

The method of claim 1, further comprising
performing a planarization process until the insulating pattern is exposed such that a remainder of the first silicon layer represents a floating gate pattern in the opening.

### Claim 8

A method of manufacturing a semiconductor device, the method comprising:
forming a mask pattern having a first opening partially exposing a surface of a substrate;
forming a trench in the substrate using the mask pattern;
forming an insulating pattern in the first opening and the trench;
removing the mask pattern to form a second opening exposing an inchoate active region of the substrate;
forming a first silicon layer, on the exposed active region and the insulating pattern, having an opened seam overlying the inchoate active region;
forming a silicon oxide layer on the first silicon layer;
heat treating the first silicon layer at a temperature sufficient to induce silicon migration so as to cause the opened seam to be closed via the silicon migration, wherein the first silicon layer is heat-treated under an atmosphere including hydrogen, and the silicon migration is promoted by a reduction reaction between hydrogen and the silicon oxide layer;
forming a second silicon layer on the first silicon layer after having closed the opened seam; and
performing a planarization process until the insulating pattern is exposed such that a remainder of the first silicon layer represents a floating gate pattern in the second opening.

### Claim 9 (depends on 8)

The method of claim 8, wherein the silicon oxide layer is formed by exposing the first silicon layer to an atmosphere including oxygen.

### Claim 10 (depends on 8)

The method of claim 8, wherein the heat treatment is performed at a temperature of about 850 to about 1000°C.

### Claim 11 (depends on 8)

The method of claim 8, wherein the first silicon layer includes impurity doped amorphous silicon and is crystallized by the heat treatment.

### Claim 12 (depends on 8)

The method of claim 8, wherein the second silicon layer includes impurity doped polysilicon.

### Claim 13 (depends on 8)

The method of claim 8, further comprising
forming a tunnel insulating layer on the exposed active region of the substrate after removing the mask pattern.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
sequentially forming a dielectric layer and a control gate conductive layer on the floating gate pattern and insulating pattern; and
sequentially patterning the control gate conductive layer, the dielectric layer, the floating gate pattern and the tunnel insulating layer so as to form a gate structure including a tunnel insulating layer pattern, a floating gate electrode, a dielectric layer pattern and a control gate electrode.