# US 7,410,862 B2 · Trench capacitor and method for fabricating the same

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- Number: US 7,410,862 B2
- Document ID: US7410862B2
- Status: Granted
- Kind: B2
- Application number: 11/380,693
- Filed: 2006-04-28
- Published: 2007-11-01
- Granted: 2008-08-12
- Earliest claimed: 2006-04-28
- Assignees: International Business Machines Corporation
- Inventors: Kangguo Cheng Cheng
- Web page: https://patentgrep.com/patent/US7410862B2

## CPC

- H10D 1/047: {of conductor-insulator-semiconductor capacitors, e.g. trench capacitors}
- A01N 25/08: containing solids as carriers or diluents
- A01N 25/12: Powders or granules (A01N25/26 takes precedence)
- A01N 59/00: Biocides, pest repellants or attractants, or plant growth regulators containing elements or inorganic compounds
- A01N 59/06: Aluminium; Calcium; Magnesium; Compounds thereof
- A01N 59/20: Copper
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- A01N: PRESERVATION OF BODIES OF HUMANS OR ANIMALS OR PLANTS OR PARTS THEREOF (preservation of food or foodstuff A23); BIOCIDES, e.g. AS DISINFECTANTS, AS PESTICIDES OR AS HERBICIDES (preparations for medical, dental or toiletry purposes which kill or prevent the growth or proliferation of unwanted organisms A61K); PEST REPELLANTS OR ATTRACTANTS; PLANT GROWTH REGULATORS

## Abstract

A trench capacitor with an isolation collar in a semiconductor substrate where the substrate adjacent to the isolation collar is free of dopants caused by auto-doping. The method of fabricating the trench capacitor includes the steps of forming a trench in the semiconductor substrate; depositing a dielectric layer on a sidewall of the trench; filling the trench with a first layer of undoped polysilicon; etching away the first layer of undoped polysilicon and the dielectric layer from an upper section of the trench whereby the semiconductor substrate is exposed at the sidewall in the upper section of the trench; forming an isolation collar layer on the sidewall in the upper section of the trench; and filling the trench with a second layer of doped polysilicon.

## Claims

### Claim 1

A method of fabricating a trench capacitor, the method comprising:
providing a semiconductor substrate;
forming a trench in the semiconductor substrate;
depositing a dielectric layer on a sidewall of the trench;
filling the trench with a first layer of undoped polysilicon;
etching away the first layer of undoped polysilicon and the dielectric layer from an upper section of the trench whereby the semiconductor substrate is exposed at the sidewall in the upper section of the trench;
forming an isolation collar layer on the sidewall in the upper section of the trench; and
filling the trench with a second layer of doped polysilicon.

### Claim 2 (depends on 1)

The method of claim 1, further including the step of doping the undoped polysilicon in a lower section of the trench after forming the isolation collar.

### Claim 3 (depends on 2)

The method of claim 2, wherein the step of doping the undoped polysilicon layer is performed by a process selected from the group consisting of solid phase doping process, liquid phase doping process, gas phase doping process, plasma doping process, plasma immersion ion implantation process, infusion doping process.

### Claim 4 (depends on 1)

The method of claim 1, including the step of forming a buried doped plate in the substrate adjacent to the lower section of the trench.

### Claim 5 (depends on 1)

The method of claim 1, including the step of forming the isolation collar layer of a first layer of oxide; and
forming a second layer of oxide on the first oxide layer of the isolation collar.

### Claim 6 (depends on 1)

The method of claim 1, wherein the step of filling the trench with an undoped polysilicon layer creates a cavity within the undoped polysilicon layer.

### Claim 7 (depends on 6)

The method of claim 6, further comprising the steps of:
removing the undoped polysilicon layer directly above said cavity, thereby forming a closed ended cavity that extends through the upper section of the trench so that the cavity is opened through the pad layer; and
filling the trench with a second doped polysilicon layer.

### Claim 8 (depends on 7)

The method of claim 7 wherein the step of removing the undoped polysilicon layer directly above said cavity is preformed with a reactive ion etching process.

### Claim 9 (depends on 8)

The method of claim 8 wherein the reactive ion etching process is performed with an etchant of SF6 and CF4.

### Claim 10 (depends on 7)

The method of claim 7, wherein the step of etching away the dielectric layer from an upper section of the trench comprises a wet etching process.

### Claim 11 (depends on 10)

The method of claim 10 wherein the wet etching process is performed with an etchant containing ammonia.

### Claim 12 (depends on 10)

The method of claim 10 wherein the wet etching process is performed with an etchant containing hydrofluoric acid and nitric acid.

### Claim 13 (depends on 1)

The method of claim 1 wherein the step of filling the trench with the first layer of undoped polysilicon comprises a process selected from the group consisting of low-pressure chemical vapor deposition process, rapid thermal deposition, and atomic layer deposition.

### Claim 14 (depends on 1)

The method of claim 1 wherein the step of filling the trench with the second layer of doped polysilicon comprises a process selected from the group consisting of low-pressure chemical vapor deposition process, rapid thermal deposition, and atomic layer deposition.

### Claim 15 (depends on 5)

The method of claim 5 wherein the step of forming the first layer of oxide of the isolation collar layer comprises a thermal oxidation process.

### Claim 16 (depends on 15)

The method of claim 15 wherein the thermal oxidation process is performed in an environment containing at least one oxygen species selected from the group consisting of oxygen (O2), nitrous oxide (N2O) nitric oxide (NO), water (H2O) and heavy water (D2O).

### Claim 17 (depends on 5)

The method of claim 5 wherein the step of forming the second oxide layer of the isolation collar comprises a process selected from the group consisting of low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, atmospheric pressure chemical vapor deposition, rapid thermal chemical vapor deposition, high-density plasma chemical vapor deposition, ozone tetra-ethyl-ortho-silicate deposition, and atomic layer deposition.