# US 7,410,853 B2 · Method of forming a nanowire and method of manufacturing a semiconductor device using the same

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- Number: US 7,410,853 B2
- Document ID: US7410853B2
- Status: Granted
- Kind: B2
- Application number: 11/431,216
- Filed: 2006-05-10
- Published: 2007-02-22
- Granted: 2008-08-12
- Earliest claimed: 2005-05-11
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Young-Joon Ahn; Choong-Ho Lee; Chul Lee
- Web page: https://patentgrep.com/patent/US7410853B2

## CPC

- H10P 50/693: {characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- B82Y 30/00: Nanotechnology for materials or surface science, e.g. nanocomposites
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- Y10S 977/938: Field effect transistors, FETS, with nanowire- or nanotube-channel region
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

In a method of forming a nanowire in a semiconductor device, a trench is formed by partially etching a bulk semiconductor substrate. An insulation layer pattern is formed on the substrate to fill up the trench. The insulation layer pattern covers a first region of the substrate where the nanowire is formed, and additionally covers a second region of the substrate connected to the first region. An opening is formed by etching an exposed portion of the substrate by the insulation layer pattern. A spacer is formed on sidewalls of the opening and the insulation layer pattern. The nanowire connected to the second region is formed by anisotropically etching a portion of the substrate exposed by the opening until a portion of the insulation layer pattern formed in the trench is exposed.

## Claims

### Claim 1

A method of forming a nanowire, comprising:
forming a trench by partially etching a semiconductor substrate;
forming an insulation layer pattern on the semiconductor substrate to fill up the trench, wherein the insulation layer pattern covers a first region of the semiconductor substrate where the nanowire is formed, and the insulation layer pattern covers a second region of the semiconductor substrate connected to the first region;
forming an opening by etching an exposed portion of the semiconductor substrate by the insulation layer pattern using the insulation layer pattern as an etching mask;
forming a spacer on sidewalls of the opening and the insulation layer pattern; and
forming the nanowire connected to the second region by anisotropically etching a portion of the semiconductor substrate exposed by the opening until a portion of the insulation layer pattern formed in the trench is exposed.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first region has a width capable of generating a volume inversion to form a channel.

### Claim 3 (depends on 2)

The method of claim 2, wherein the first region has the width below about 5 nm.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming the trench further comprises:
forming a first hard mask pattern on the semiconductor substrate; and
partially etching the semiconductor substrate using the first hard mask pattern as an etching mask.

### Claim 5 (depends on 4)

The method of claim 4, wherein forming the insulation layer pattern further comprises:
forming a second hard mask pattern exposing a portion of the first region adjacent to the trench by partially etching the first hard mask pattern;
forming a first preliminary insulation layer pattern on the exposed portion of the first region to fill up the trench;
forming an opening exposing the second region and a third hard mask pattern covering the first region except for the exposed portion of the first region by partially etching the second hard mask pattern and the first preliminary insulation layer pattern;
forming a second preliminary insulation layer pattern to fill up the opening; and
removing the third hard mask pattern.

### Claim 6 (depends on 5)

The method of claim 5, wherein the second hard mask pattern is formed by an anisotropic etching process.

### Claim 7 (depends on 5)

The method of claim 5, wherein an etched amount of the first hard mask pattern is substantially the same as a width of a channel that generates a volume inversion.

### Claim 8 (depends on 5)

The method of claim 5, wherein forming the second preliminary insulation layer pattern further comprises:
forming a second preliminary insulation layer to completely fill up the opening; and
partially removing the second preliminary insulation layer until the third hard mask pattern is exposed.

### Claim 9 (depends on 1)

The method of claim 1, wherein the opening has a depth substantially the same as a width of a channel that generates a volume inversion.

### Claim 10 (depends on 1)

The method of claim 1, wherein the spacer is formed using a material having an etching selectivity relative to the semiconductor substrate.

### Claim 11 (depends on 10)

The method of claim 10, wherein the spacer is formed using silicon oxide.

### Claim 12 (depends on 1)

The method of claim 1, wherein forming the nanowire is performed by a wet etching process or a chemical dry etching process.

### Claim 13 (depends on 1)

The method of claim 1, further comprising partially etching the insulation layer pattern and completely etching the spacer to expose the nanowire.

### Claim 14

A method of manufacturing a semiconductor device, comprising:
forming a trench by partially etching a semiconductor substrate;
forming a first insulation layer pattern on the semiconductor substrate to fill up the trench, wherein the first insulation layer pattern covers a source/drain formation region of the semiconductor substrate, and the first insulation layer pattern covers a nanowire formation region of the semiconductor substrate connected to the source/drain formation region;
forming an opening by etching an exposed portion of the semiconductor substrate by the first insulation layer pattern using the first insulation layer pattern as an etching mask;
forming a spacer on sidewalls of the opening and the first insulation layer pattern;
forming the nanowire connected to the source/drain formation region by anisotropically etching a portion of the semiconductor substrate exposed by the opening until a portion of the first insulation layer pattern formed in the trench is exposed;
forming a second insulation layer pattern by partially etching the first insulation layer pattern and fully etching the spacer until the nanowire is exposed;
forming a gate insulation layer on the semiconductor substrate to cover the nanowire; and
forming a gate electrode on the gate insulation layer to enclose the nanowire.

### Claim 15 (depends on 14)

The method of claim 14, wherein the nanowire formation region has a width that generates a volume inversion in a channel.

### Claim 16 (depends on 14)

The method of claim 14, further comprising forming an impurity region having a high impurity concentration at a portion of the semiconductor substrate exposed through the opening the after forming the spacer.

### Claim 17 (depends on 16)

The method of claim 16, wherein the impurity region is separated from a bottom face of the opening by a distance substantially the same as a width of the nanowire.

### Claim 18 (depends on 16)

The method of claim 16, wherein the impurity region has a conductivity type opposite to a conductivity type of the semiconductor device.

### Claim 19 (depends on 14)

The method of claim 14, wherein forming the trench further comprises:
forming a first hard mask pattern on the semiconductor substrate; and
partially etching the semiconductor substrate using the first hard mask pattern as an etching mask.

### Claim 20 (depends on 19)

The method of claim 19, wherein forming the first insulation layer pattern further comprises:
forming a second hard mask pattern exposing a portion of the nanowire formation region adjacent to the trench by partially etching the first hard mask pattern;
forming a first preliminary insulation layer pattern on the exposed portion of the nanowire formation region to fill up the trench;
forming an opening exposing the source/drain formation region and forming a third hard mask pattern covering the nanowire formation region except for the exposed portion of the nanowire formation region by partially etching the second hard mask pattern and the first preliminary insulation layer pattern;
forming a second preliminary insulation layer pattern to fill up the opening; and
removing the third hard mask pattern.

### Claim 21 (depends on 20)

The method of claim 20, wherein an etched amount of the first hard mask pattern is substantially the same as a width of a channel that generates a volume inversion.

### Claim 22 (depends on 14)

The method of claim 14, wherein the opening has a depth substantially the same as a width of a channel that generates a volume inversion.

### Claim 23 (depends on 14)

The method of claim 14, further comprising forming source/drain regions by implanting impurities into the source/drain formation region.

### Claim 24 (depends on 14)

The method of claim 14, wherein partially etching the first insulation layer pattern and fully etching the spacer are performed by a wet etching process.