# US 7,410,852 B2 · Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors

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- Number: US 7,410,852 B2
- Document ID: US7410852B2
- Status: Granted
- Kind: B2
- Application number: 11/408,522
- Filed: 2006-04-21
- Published: 2007-10-25
- Granted: 2008-08-12
- Earliest claimed: 2006-04-21
- Assignees: International Business Machines Corporation
- Inventors: Scott D. Allen; Cyril Cabral, Jr.; Kevin K. Dezfulian; Sunfei Fang; Brian J. Greene; Rajarao Jammy; Christian Lavoie; Zhijiong Luo; Hung Ng; Chun-Yung Sung; Clement H. Wann; Huilong Zhu
- Web page: https://patentgrep.com/patent/US7410852B2

## CPC

- H10P 34/42: with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20)
- H10D 30/0212: {using self-aligned silicidation}
- H10D 64/01316: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/0132: {the conductor being a metallic silicide}
- H10D 64/01338: {with a treatment, e.g. annealing, after the formation of the conductor}
- H10P 34/422: {using incoherent radiation}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.

## Claims

### Claim 1

A method for fabricating a field effect transistor comprising:
forming a stack layer comprising a suicide forming metal contacting a silicon layer over a semiconductor substrate, said suicide forming metal selected from the group consisting of cobalt, nickel, platinum, tungsten, titanium and their alloys;
forming a source/drain region into the semiconductor substrate while using at least the stack layer as a mask;
forming a thermal insulator layer upon the source/drain region;
forming a thermal absorber layer comprises an amorphous carbon material, upon the stack layer; and
selectively opto-thermally annealing the stack layer to form a fully silicide gate electrode while not annealing the source/drain region, said opt-thermally annealing is performed at a temperature from about 1000° to about 1400° centigrade and for a time period from about 0.01 to about 100 milliseconds.