# US 7,410,844 B2 · Device fabrication by anisotropic wet etch

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- Number: US 7,410,844 B2
- Document ID: US7410844B2
- Status: Granted
- Kind: B2
- Application number: 11/333,108
- Filed: 2006-01-17
- Published: 2007-07-19
- Granted: 2008-08-12
- Earliest claimed: 2006-01-17
- Assignees: International Business Machines Corporation
- Inventors: Yujun Li; Kenneth T. Settlemyer, Jr.; Jochen Beintner
- Web page: https://patentgrep.com/patent/US7410844B2

## CPC

- H10D 86/01: Manufacture or treatment
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/405: {Orientations of crystalline planes}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10P 50/644: {Anisotropic liquid etching (H10P50/61 takes precedence)}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.

## Claims

### Claim 1

A method for fabricating a field effect device, comprising:
producing a pedestal by forming a trench in a monocrystalline Si layer of a SOI wafer, said pedestal having a top surface and a plurality of sidewalls, wherein said top surface and said plurality of sidewalls are so oriented as to be substantially parallel with crystallographic planes of said layer of said SOI wafer, wherein said top surface is oriented to be substantially parallel with a {100}crystallographic plane of said layer of said SOI wafer;
wet etching said pedestal with a mixture of water and ammonium hydroxide (NH4OH), wherein selecting the ratio of water to ammonium hydroxide to be between about 15:1 and about 200:1, and the temperature of said mixture to be between about 25° C. and about 70° C., wherein due to differing etch rates of crystallographic planes in said solution said plurality of sidewalls become faceted, wherein said faceting creates a reduced cross section segment on said pedestal;
preventing said wet etching of said top surface by covering said top surface with a dielectric layer;
preventing said wet etching of said plurality of sidewalls alongside a strip by covering said strip with a dielectric layer, wherein said strip borders said top surface; and
in said reduced cross section segment, selecting a dopant concentration such that said reduced cross section segment is electrically conductive, wherein allowing for electrical continuity between said field effect device and said layer of said SOI wafer, wherein said field effect device is electrically coupled to said top surface; and
completing fabrication of said field effect device.