# US 7,410,841 B2 · Building fully-depleted and partially-depleted transistors on same chip

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- Number: US 7,410,841 B2
- Document ID: US7410841B2
- Status: Granted
- Kind: B2
- Application number: 11/091,249
- Filed: 2005-03-28
- Published: 2006-09-28
- Granted: 2008-08-12
- Earliest claimed: 2005-03-28
- Assignees: Texas Instruments Incorporated
- Inventors: Howard Lee Tigelaar
- Web page: https://patentgrep.com/patent/US7410841B2

## CPC

- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- Y10S 438/977: Thinning or removal of substrate
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A method (10) of forming fully-depleted silicon-on-insulator (FD-SOI) transistors (150) and partially-depleted silicon-on-insulator (FD-SOI) transistors (152) on a semiconductor substrate (104) as part of an integrated circuit fabrication process is disclosed.

## Claims

### Claim 1

A method of forming a fully-depleted silicon-on-insulator (FD-SOI) transistor and a partially-depleted silicon-on-insulator (PD-SOI) transistor as part of an integrated circuit fabrication process, comprising:
providing a silicon-on-insulator (SOI) substrate which comprises a layer of silicon material formed over a layer of insulating material which is formed over a semiconductor substrate;
thinning the layer of silicon material to a thickness suitable for forming a partially-depleted transistor by growing a first grown layer of oxide material over the layer of silicon material, where growing the first grown layer of oxide material thins the layer of silicon material by consuming silicon as part of the growth process;
forming a layer of nitride material over the first grown layer of oxide material;
patterning the layer of nitride material, the first grown layer of oxide material and the layer of silicon material to establish trenches therein;
depositing a layer of dielectric material that fills in the trenches;
planarizing the deposited layer of dielectric material;
masking off an area of the SOI substrate wherein the partially-depleted transistor is to be formed;
removing the layer of nitride material in an area where the fully-depleted transistor is to be formed;
removing the first grown layer of oxide material in the area where fully-depleted transistor is to be formed;
unmasking the area of the SOI substrate where the partially-depleted transistor is to be formed;
thinning the layer of silicon material in the area where the fully-depleted transistor is to be formed to a thickness suitable for forming the fully-depleted transistor by growing a second grown layer of oxide material over the layer of silicon material, where growing the second grown layer of oxide material thins the layer of silicon material by consuming silicon as part of the growth process;
removing the layer of nitride material in the area where the partially-depleted transistor is to be formed;
removing the first grown layer of oxide material in the area where the partially-depleted transistor is to be formed and removing the second growth layer of oxide material in the area where the fully-depleted transistor is to be formed; and
forming the partially-depleted transistor in the area where the partially-depleted transistor is to be formed and forming the fully-depleted transistor in the area where the fully-depleted transistor is to be formed.

### Claim 2 (depends on 1)

The method of claim 1, wherein the area where the partially-depleted transistor is to be formed is masked off with a resist material.

### Claim 3 (depends on 1)

The method of claim 1, wherein the layer of silicon material in the area where the fully-depleted transistor is to be formed is thinned via etching rather than growing the second grown layer of oxide material.

### Claim 4 (depends on 1)

The method of claim 1, wherein layer of dielectric material that fills in the trenches is deposited via chemical vapor deposition (CVD).

### Claim 5 (depends on 1)

The method of claim 1, wherein the layer of silicon material is formed to a thickness of between around 800 Angstroms and around 1200 Angstroms.

### Claim 6 (depends on 1)

The method of claim 1, wherein the layer of nitride material is formed to thickness of between around 700 Angstroms and around 800 Angstroms.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first grown layer of oxide material thins to layer of silicon material down to a thickness of between around 800 Angstrom and around 1000 Angstroms.

### Claim 8 (depends on 1)

The method of claim 1, wherein the second grown layer of oxide material thins the layer of silicon material down to a thickness of between around 50 Angstroms and around 200 Angstroms.

### Claim 9 (depends on 1)

The method of claim 1, wherein the deposited dielectric material is planarized via chemical mechanical polishing (CMP).

### Claim 10 (depends on 1)

The method of claim 1, wherein at least one of;
a plasma etch is used to remove the layer of nitride material in the area where the fully-depleted transistor is to be formed,
a plasma etch is used to remove the layer of nitride material in the area where the partially-depleted transistor is to be formed,
a hydrogen fluoride (HF) based substance is used to remove the first grown layer of oxide material in the area where fully-depleted transistor is to be formed,
a hydrogen fluoride (HF) based substance is used to remove the first grown layer of oxide material in the area where the partially-depleted transistor is to be formed, and
a hydrogen fluoride (HF) based substance is used to remove the second grown layer of oxide material in the area where the fully-depleted transistor is to be formed.

### Claim 11 (depends on 1)

The method of claim 1, wherein
forming the fully-depleted transistor comprises forming a fully-depleted gate structure over the thinned silicon in the area where the fully-depleted transistor is to be formed, forming a source region within the thinned silicon adjacent to one side of the fully-depleted gate structure and forming a drain region within the thinned silicon adjacent to the other side of the fully-depleted gate structure, and
forming the partially-depleted transistor comprises forming a partially-depleted gate structure over the thinned silicon in the area where the partially-depleted transistor is to be formed, forming a source region within the thinned silicon adjacent to one side of the partially-depleted gate structure and forming a drain region within the thinned silicon adjacent to the other side of the partially-depleted gate structure.

### Claim 12 (depends on 11)

The method claim 11, wherein the fully-depleted gate structure comprises a gate dielectric and a gate electrode, and the partially-depleted gate structure comprises a gate dielectric and a gate electrode.

### Claim 13

A method of forming a fully-depleted silicon-on-insulator (FD-SOI) transistor and a partially-depleted silicon-on-insulator (PD-SOI) transistor as part of an integrated circuit fabrication process, comprising:
providing a silicon-on-insulator (SOI) substrate which comprises a layer of silicon material formed over a layer of insulating material which is in turn formed over a semiconductor substrate;
converting at least some of the SOI substrate into an area where the partially-depleted transistor can be formed and converting at least some of the SOI substrate into an area where the fully-depleted transistor can be formed, wherein the converting comprises:
removing a portion of the layer of silicon material to form a trench therein which separates the area where the partially-depleted transistor can be formed from the area where the fully-depleted transistor can be formed;
forming an insulation material in the trench wherein the insulation material contacts an oxidation inhibitor layer which overlies the area where the partially-depleted transistor can be formed and the area where the fully-depleted transistor can be formed in the insulation material; and
forming the partially-depleted transistor in the area where the partially-depleted transistor can be formed and forming the fully-depleted transistor in the area where the fully-depleted transistor can be formed.

### Claim 14 (depends on 13)

The method of claim 13, wherein converting at least some of the SOI substrate into an area where the partially-depleted transistor can be formed further comprises:
thinning the layer of silicon material to a thickness suitable for forming a partially-depleted transistor.

### Claim 15 (depends on 14)

The method of claim 14, wherein converting at least some of the SOI substrate into an area where the fully-depleted transistor can be formed further comprises:
further thinning the layer of silicon material in the area where the fully-depleted transistor can be formed to a thickness suitable for forming a fully-depleted transistor.

### Claim 16 (depends on 15)

The method of claim 15, wherein the layer of silicon material is thinned by growing a first grown layer of oxide material which consumes silicon as part of the growth process, and removing the first grown layer of oxide material to reveal the thinned silicon.

### Claim 17 (depends on 16)

The method of claim 16, wherein the layer of silicon material is further thinned in the area where the fully-depleted transistor can be formed by at least one of;
growing a second grown layer of oxide material in the area where the fully-depleted transistor can be formed, where growing the oxide consumes silicon as part of the growth process, and removing the second grown layer of oxide material to reveal the further thinned silicon; and
etching the layer of silicon material in the area where the fully-depleted transistor can be formed to further thin the layer of silicon material.

### Claim 18 (depends on 17)

The method of claim 17, wherein the layer of silicon material is thinned down to a thickness of between around 800 Angstroms and around 1000 Angstroms, and wherein the layer of silicon is further thinned down to a thickness of between around 50 Angstroms and around 200 Angstroms in the area where the fully-depleted transistor can be formed.

### Claim 19 (depends on 13)

The method of claim 13, further comprising forming the insulation material over the area where the partially-depleted transistor can be formed and over the area where the fully-depleted transistor can be formed wherein, in cross section, the insulation material surrounds the oxidation inhibitor layer.

### Claim 20 (depends on 19)

The method of claim 19, further comprising removing the oxidation inhibitor from over the area where the fully-depleted transistor can be formed and leaving the oxidation inhibitor over the area where the partially-depleted transistor can be formed.

### Claim 21 (depends on 20)

The method of claim 20 further comprising oxidizing the layer of silicon where the fully-depleted transistor can be formed, wherein the oxidation inhibitor inhibits oxidation of the layer of silicon where the partially-depleted transistor can be formed.