# US 7,410,832 B2 · Semiconductor chip package having an adhesive tape attached on bonding wires > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,410,832 B2 - Document ID: US7410832B2 - Status: Granted - Kind: B2 - Application number: 11/727,298 - Filed: 2007-03-26 - Published: 2007-08-16 - Granted: 2008-08-12 - Earliest claimed: 2002-09-13 - Assignees: Samsung Electronics Co., Ltd. - Inventors: Sang-Yeop Lee; Min-Il Kim - Web page: https://patentgrep.com/patent/US7410832B2 ## CPC - H10W 90/00: Package configurations - H05K 13/0469: {by applying a glue or viscous material} - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 72/015: {of bond wires} - H10W 72/01515: {Forming coatings} - H10W 72/075: {of bond wires} - H10W 72/536: {the connected ends being ball-shaped} - H10W 72/5363: {the connected ends being wedge-shaped} - H10W 72/5366: {the bond wires having kinks} - H10W 72/581: {Auxiliary members, e.g. flow barriers} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/951: {Materials of bond pads} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/231: {the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure} - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract The invention provides a semiconductor chip package, and a means of forming such a semiconductor chip package, in which one or more semiconductor chips are electrically connected to a mounting substrate by wire bonding in which an adhesive tape is provided on the active surface of the semiconductor chips for encapsulating at least an upper portion of the bonding wires adjacent the active surfaces to improve the stability of the bonding wires during subsequent processing. ## Claims ### Claim 1 A method of assembling a semiconductor chip package comprising: attaching a first semiconductor chip having a first surface and an active surface opposite the first surface on a mounting means; attaching a first plurality of bonding wires between chip pads arrayed within a perimeter of the active surface of the first semiconductor chip and mount pads arrayed on the mounting means, the first plurality of bonding wires establishing electrical connections between the first semiconductor chip and the mounting means; attaching a first adhesive tape to the active surface of the first semiconductor chip and to upper portions of the first plurality of bonding wires; and heating the first adhesive tape to a temperature sufficient to cause portions of the first adhesive tape to encapsulate the upper portions of the bonding wires within the first adhesive tape. ### Claim 2 (depends on 1) A method of assembling a semiconductor chip package according to claim 1, wherein heating the first adhesive tape is accomplished using at least one heating technique selected from thermo-compression, radiation, conduction and convection. ### Claim 3 (depends on 1) A method of assembling a semiconductor chip package according to claim 1, further comprising: encapsulating the first semiconductor chip, the first plurality of bonding wires and the first adhesive tape in a polymeric composition; and curing the polymeric composition. ### Claim 4 (depends on 1) A method of assembling a semiconductor chip package according to claim 1, further comprising: attaching a second semiconductor chip having a first surface and an active surface opposite the first surface to the first semiconductor chip, the attachment being substantially maintained by the first adhesive tape; attaching a second plurality of bonding wires between chip pads arrayed within a perimeter of the active surface of the second semiconductor chip and mount pads arrayed on the mounting means, the second plurality of bonding wires establishing electrical connections between the second semiconductor chip and the mounting means; attaching a second adhesive tape to the active surface of the second semiconductor chip and to upper portions of the second plurality of bonding wires; and heating the second adhesive tape to a temperature sufficient to encapsulate the upper portions of the second plurality of bonding wires within the second adhesive tape. ### Claim 5 (depends on 4) A method of assembling a semiconductor chip package according to claim 4, wherein: heating the first adhesive tape to encapsulate the first plurality of bonding wires and heating the second adhesive tape to encapsulate the second plurality of bonding wires are performed substantially simultaneously. ### Claim 6 (depends on 4) A method of assembling a semiconductor chip package according to claim 4, wherein heating the first adhesive tape is conducted at a first temperature and heating the second adhesive tape is conducted at a second temperature; wherein the second temperature is insufficient to cause the first adhesive tape to encapsulate the first plurality of bonding wires. ### Claim 7 (depends on 4) A method of assembling a semiconductor chip package according to claim 4 producing a semiconductor chip package further comprising, heating the second adhesive tape to a temperature sufficient to encapsulate the upper portions of the second plurality of bonding wires within the second adhesive tape. ### Claim 8 (depends on 1) A method of assembling a semiconductor chip package according to claim 1 producing a semiconductor chip package comprising: a first semiconductor chip having a first surface and an active surface opposite the first surface; chip pads arrayed within a perimeter of the active surface; a mounting means having a mounting region to which the first surface of the semiconductor chip is affixed and a plurality of mount pads arrayed on the mounting means; first plurality of bonding wires providing electrical connection between chip pads and mount pads, upper portions of the first plurality of bonding wires extending from the chip pads and above and across a peripheral region of the active surface; and a first adhesive tape attached to the active surface of the first semiconductor chip and substantially encapsulating the upper portions of the first plurality of bonding wires. ### Claim 9 (depends on 1) A method of assembling a semiconductor chip package according to claim 1 producing a semiconductor chip package further comprising, heating the first adhesive tape to a temperature sufficient to cause portions of the first adhesive tape to encapsulate the upper portions of the bonding wires within the first adhesive tape.