# US 7,408,269 B2 · Multi-level power supply system for a complementary metal oxide semiconductor circuit

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- Number: US 7,408,269 B2
- Document ID: US7408269B2
- Status: Granted
- Kind: B2
- Application number: 10/867,094
- Filed: 2004-06-14
- Published: 2005-12-15
- Granted: 2008-08-05
- Earliest claimed: 2004-06-14
- Assignees: International Business Machines Corporation
- Inventors: Rajiv V Joshi; Louis L Hsu
- Web page: https://patentgrep.com/patent/US7408269B2

## CPC

- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C)
- G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

There is provided a method for managing a multi-level power supply. The method includes comparing a voltage level (Vs1) of a lower voltage supply bus to a voltage level (Vs2) of a higher voltage supply bus, and routing current from the lower voltage supply bus to the higher voltage supply bus if Vs2<Vs1. The lower and higher voltage supply busses provide power to a complementary metal oxide semiconductor (CMOS) circuit. The method prevents a latch-up of the CMOS circuit. There is also provided a circuit that employs the method.

## Claims

### Claim 1

A method comprising:
comparing a voltage level (Vs1) of a lower voltage supply bus to a voltage level (Vs2) of a higher voltage supply bus; and
routing current from said lower voltage supply bus to said higher voltage supply bus if Vs2<Vs1,
wherein said comparing is performed by a device that is powered by said lower voltage supply bus,
wherein said lower and higher voltage supply busses provide power to a circuit that includes a plurality of p-type metal oxide semiconductor devices in a common well, and
wherein said common well is electrically connected to said higher voltage supply bus.

### Claim 2 (depends on 1)

The method of claim 1, wherein said routing of said current continues until Vs2≧Vs1.

### Claim 3 (depends on 1)

The method of claim 1, wherein said circuit is a complementary metal oxide semiconductor (CMOS) circuit.

### Claim 4 (depends on 1)

The method of claim 1,
wherein said lower voltage supply bus is a first voltage supply bus,
wherein said higher voltage supply bus is a second voltage supply bus, and
wherein said method further comprises:
comparing Vs2 to a voltage level (Vs3) of a third voltage supply bus; and
routing current from said second voltage supply bus to said third voltage supply bus if Vs3<Vs2.

### Claim 5 (depends on 4)

The method of claim 4,
wherein said third voltage supply bus also provides power to said circuit, and
wherein said circuit operates with Vs3>Vs2>Vs1.

### Claim 6 (depends on 1)

The method of claim 1, wherein said comparing is performed by a device having inputs for sensing Vs1 and Vs2, and that employs hysteresis to said inputs.