# US 7,408,246 B2 · Controlling warping in integrated circuit devices

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- Number: US 7,408,246 B2
- Document ID: US7408246B2
- Status: Granted
- Kind: B2
- Application number: 11/095,929
- Filed: 2005-03-31
- Published: 2006-10-05
- Granted: 2008-08-05
- Earliest claimed: 2005-03-31
- Assignees: Agere Systems Inc.
- Inventors: John W. Osenbach; Thomas H. Shilling; Weidong Xie
- Web page: https://patentgrep.com/patent/US7408246B2

## CPC

- H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates}
- H10W 72/30: Die-attach connectors
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.

## Claims

### Claim 1

An integrated circuit device comprising:
a base;
at least one die attached to the base; and
a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die, wherein said counterbalancing layer comprises at least one metal.

### Claim 2 (depends on 1)

The device of claim 1, comprising a power transistor device.

### Claim 3 (depends on 1)

The device of claim 1, wherein the thermal expansion difference occurs as a result of heat generated during attachment of the die to the base.

### Claim 4 (depends on 1)

The device of claim 1, wherein the die is attached to the base by soldering.

### Claim 5 (depends on 1)

The device of claim 1, wherein the thermal expansion difference between the base and the die is due, at least in part, to the base having a different coefficient of thermal expansion from the die.

### Claim 6 (depends on 1)

The device of claim 1, wherein the die comprises one or more of silicon, indium phosphide, indium gallium phosphide, indium gallium arsenide phosphide, gallium arsenide, silicon carbide, silica germanium, indium tin oxide, black diamond, crystallized carbon, polymeric semiconductor and lithium niobate.

### Claim 7 (depends on 1)

The device of claim 1, wherein the base comprises one or more metals.

### Claim 8 (depends on 1)

The device of claim 1, wherein the base comprises one or more of copper and alloys thereof.

### Claim 9 (depends on 1)

The device of claim 1, wherein the counterbalancing layer comprises one or more of nickel and gold.

### Claim 10 (depends on 1)

The device of claim 1, wherein the counterbalancing layer is segmented, having indentations on at least one surface thereof.

### Claim 11 (depends on 1)

The device of claim 1, wherein the counterbalancing layer is segmented, having perforations extending through the entire thickness of the layer, the length of each segment running parallel with a direction of warping.

### Claim 12 (depends on 1)

The device of claim 1, wherein the counterbalancing layer comprises a hatched layer.

### Claim 13 (depends on 1)

The device of claim 1, wherein the counterbalancing layer is applied as a continuous layer extending substantially over at least one side of the base.

### Claim 14 (depends on 1)

The device of claim 1, wherein the counterbalancing layer is applied to a side of the base opposite the die.

### Claim 15 (depends on 1)

The device of claim 1, wherein the counterbalancing layer has a thickness of about five micrometers to about 100 micrometers.

### Claim 16

A method of controlling warping of a power transistor device comprising at least one die attached to a base, the method comprising the step of:
applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die, wherein said counterbalancing layer comprises at least one metal.