# US 7,408,240 B2 · Memory device

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- Number: US 7,408,240 B2
- Document ID: US7408240B2
- Status: Granted
- Kind: B2
- Application number: 11/120,007
- Filed: 2005-05-02
- Published: 2006-11-02
- Granted: 2008-08-05
- Earliest claimed: 2005-05-02
- Assignees: Infineon Technologies AG
- Inventors: Shoaib Hasan Zaidi
- Web page: https://patentgrep.com/patent/US7408240B2

## CPC

- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/068: {by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers}
- H10N 70/8265: {on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices}
- H10N 70/8413: {adapted for resistive heating}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A phase change memory cell is disclosed. The phase change memory cell includes a first thin film spacer and a second thin film spacer. The first thin film spacer defines a sub-lithographic dimension and is electrically coupled to a first electrode. The second thin film spacer defines a sub-lithographic dimension and is electrically coupled between a second electrode and the first thin film spacer. In this regard, the phase change memory cell is formed at a boundary where the first thin film spacer electrically contacts the second thin film spacer.

## Claims

### Claim 1

An integrated circuit having a resistivity changing cell comprising:
a first thin film spacer defining a sub-lithographic dimension and electrically coupled to a first electrode; and
a second thin film spacer defining a sub-lithographic dimension;
wherein the resistivity changing cell is formed at a boundary where the first thin film spacer electrically contacts the second thin film spacer; and
wherein the first thin film spacer comprises one of titanium nitride and a resistivity changing material.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the boundary where the first thin film spacer electrically contacts the second thin film spacer defines a sub-lithographic contact area of between approximately 18-22 nanometers square.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein the first thin film spacer defines a first sidewall and the second thin film spacer defines a second sidewall, and further wherein the first sidewall is orthogonal to the second sidewall and the first thin film spacer is disposed at a tilt angle relative to the second thin film spacer.

### Claim 4 (depends on 3)

The integrated circuit of claim 3, wherein the first thin film spacer is disposed at a tilt angle of between 70-110 degrees relative to the second thin film spacer, and further wherein the first thin film spacer contacts the second thin film spacer across an area of between approximately 18-22 nanometers square.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, wherein the second thin film spacer comprises a chalcogenic phase change material.

### Claim 6

A memory device comprising:
an array of phase change memory cells disposed on a chip and defined by:
a plurality of first spacers extending in a first direction, each first spacer defining a sub-lithographic dimension and in electrical contact with a respective first electrode; and
a plurality of second spacers extending in a second direction non-parallel to the first direction, each second spacer including phase change material and defining a sub-lithographic dimension, each second spacer in electrical contact with a respective second electrode and a respective one of the first spacers;
wherein a phase change memory cell is formed at each intersection of each respective first spacer with each respective second spacer.

### Claim 7 (depends on 6)

The memory device of claim 6, wherein the first spacers comprise titanium nitride.

### Claim 8 (depends on 6)

The memory device of claim 6, wherein the second spacers comprise chalcogenic phase change material.

### Claim 9 (depends on 6)

The memory device of claim 6, wherein the second spacers comprise stratified layers of chalcogenic phase change material, and further wherein electrical resistivity varies between the stratified layers of chalcogenic phase change material.

### Claim 10 (depends on 6)

The memory device of claim 6, wherein the second spacers extend in a second direction approximately orthogonal to the first direction.

### Claim 11 (depends on 6)

The memory device of claim 6, wherein the second spacers extend in a second direction that is minimally skewed from a parallel orientation relative to the first direction.

### Claim 12 (depends on 10)

The memory device of claim 10, wherein the second spacers contact the first spacers across an area between approximately 18-22 nanometers square.

### Claim 13 (depends on 6)

The memory device of claim 6, wherein the second spacers are tilted at an angle of between 70 and 110 degrees relative to the first spacers.

### Claim 14 (depends on 13)

The memory device of claim 13, wherein the second spacers are tilted at an angle of approximately 78 degrees relative to the first spacers, and further wherein the second spacers contact the first spacers across an area between approximately 18-22 nanometers square.

### Claim 15

An electronic system comprising:
an electronic device; and
a memory device electrically coupled to the electronic device, the memory device comprising at least one phase change memory cell defining:
a first thin film spacer defining a sub-lithographic dimension and electrically coupled to a first electrode,
a second thin film spacer defining a sub-lithographic dimension and electrically coupled between a second electrode and the first thin film spacer;
wherein the at least one phase change memory cell is formed at a boundary where the first thin film spacer electrically contacts the second thin film spacer; and
wherein the first thin film spacer comprises one of titanium nitride and a resistivity changing material.

### Claim 16 (depends on 15)

The electronic system of claim 15, wherein the first thin film spacer electrically contacts the second thin film spacer across .a contact area of between approximately 18-22 nanometers square of the memory cell.

### Claim 17 (depends on 15)

The electronic system of claim 15, wherein the first thin film spacer is disposed at a tilt angle relative to the second thin film spacer.

### Claim 18

An integrated circuit having a resistivity changing cell comprising:
a first thin film spacer defining a sub-lithographic dimension and electrically coupled to a first electrode; and
a second thin film spacer defining a sub-lithographic dimension;
wherein the resistivity changing cell is formed at a boundary where the first thin film spacer electrically contacts the second thin film spacer; and
wherein the boundary where the first thin film spacer electrically contacts the second thin film spacer defines a sub-lithographic contact area of between approximately 18-22 nanometers square.

### Claim 19

An integrated circuit having a resistivity changing cell comprising:
a first thin film spacer defining a sub-lithographic dimension and electrically coupled to a first electrode; and
a second thin film spacer defining a sub-lithographic dimension;
wherein the resistivity changing cell is formed at a boundary where the first thin film spacer electrically contacts the second thin film spacer; and
wherein the first thin film spacer defines a first sidewall and the second thin film spacer defines a second sidewall, and further wherein the first sidewall is orthogonal to the second sidewall and the first thin film spacer is disposed at a tilt angle relative to the second thin film spacer.

### Claim 20

An integrated circuit having a resistivity changing cell comprising:
a first thin film spacer defining a sub-lithographic dimension and electrically coupled to a first electrode; and
a second thin film spacer defining a sub-lithographic dimension;
wherein the resistivity changing cell is formed at a boundary where the first thin film spacer electrically contacts the second thin film spacer; and
wherein the first thin film spacer is disposed at a tilt angle of between 70-110 degrees relative to the second thin film spacer, and further wherein the first thin film spacer contacts the second thin film spacer across an area of between approximately 18-22 nanometers square.