# US 7,408,239 B2 · Capture of residual refractory metal within semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,408,239 B2 - Document ID: US7408239B2 - Status: Granted - Kind: B2 - Application number: 11/650,978 - Filed: 2007-01-09 - Published: 2007-05-24 - Granted: 2008-08-05 - Earliest claimed: 2001-03-30 - Assignees: Renesas Technology Corp. - Inventors: Takeshi Kamino; Toshiaki Tsutsumi; Shuji Kodama; Takio Ohno - Web page: https://patentgrep.com/patent/US7408239B2 ## CPC - H10D 1/474: {comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides} - H10D 84/209: {of only resistors} - H10W 76/48: Fillings including materials for absorbing or reacting with moisture or other undesired substances - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract There is provided a semiconductor device with a configuration in which a dummy silicide area 11 is provided in the vicinity of a non-silicide area 2 to easily capture residual refractory metals, resulting in an improved yield by preventing the trapping of residual refractory metals into a non-silicide area and thereby reducing a junction leakage within the non-silicide area. ## Claims ### Claim 1 A semiconductor device, comprising: a semiconductor substrate; a first, a second and a third diffusion resistors formed in said semiconductor substrate and arranged in parallel to each other, and each diffusion resistor having a top surface, a first end and a second end opposing said first end; an isolation dielectric film surrounding each of said first, second and third diffusion resistors in plan view; a first silicide film formed on said top surface of said first and third diffusion resistors; and a second silicide film formed on said top surface of said second diffusion resistor, wherein said second diffusion resistor is arranged between said first and third diffusion resistors, and wherein said first silicide film covers a whole top surface of said first and third diffusion resistors, and said second silicide film partially covers the top surface of said second diffusion resistor at said first and second ends and a portion between said first and second ends of said second diffusion resistor is not covered with said second silicide film, and wherein the first silicide and the second silicide are CoSi. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein said second diffusion resistor includes a pair of diffusion resistors arranged in parallel between said first and third diffusion resistors. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, further comprising a fourth diffusion resistor formed in said semiconductor substrate and arranged in parallel to said first, second, and third diffusion resistors, said fourth diffusion resistor having a top surface, a first end and a second end opposing said first end, a third silicide film partially covers the top surface of the fourth resistor at said first and second ends and at regular intervals therebetween, said fourth diffusion resistor positioned between the pair of diffusion resistors. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein the silicide formed is formed within 200 microns or less with respect to the portion which is not covered. ### Claim 5 (depends on 2) The semiconductor device according to claim 2, wherein the silicide form is formed within 200 microns or less with respect to said portion which is not covered. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the silicide film is formed within 200 microns or less with respect to the portion not covered. ### Claim 7 A semiconductor device comprising: a semiconductor substrate; a plurality of diffusion resistors formed in said semiconductor substrate and arranged in parallel to each other, and each diffusion resistor having a top surface, a first end and a second end opposing said first end; an isolation dielectric film surrounding each diffusion resistor in plan view; and a plurality of silicide films partially cover the top surface of each diffusion resistor at said first and second ends and at regular intervals between the first and second ends, wherein the silicide is CoSi. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, further comprising at least two additional diffusion resistors formed in said semiconductor substrate and arranged in parallel to said plurality of diffusion resistors, each additional diffusion resistor having a top surface, and an additional silicide film formed on a whole top surface of said each additional diffusion resistor, and at least some of said plurality of diffusion resistors arranged between said at least two additional diffusion resistors. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein a length of each non-silicide area of each diffusion resistor between the regular intervals is 200 microns or less. ### Claim 10 (depends on 7) The semiconductor device according to claim 7, wherein a length of each non-silicide area between the regular intervals is 200 microns or less. ### Claim 11 A semiconductor device comprising: a semiconductor substrate; a plurality of diffusion resistors formed in said semiconductor substrate and arranged in parallel to each other, an isolation dielectric film surrounding each diffusion resistor in plan view; each diffusion resistor formed by a plurality of separate areas to be connected in series; and a silicide film partially covers a top surface of each separate area at first and second ends of each separate area and a portion between said first and second ends of each separate area is not covered by the silicide film, wherein the silicide is CoSi.