# US 7,408,234 B2 · Semiconductor device and method for manufacturing the same

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- Number: US 7,408,234 B2
- Document ID: US7408234B2
- Status: Granted
- Kind: B2
- Application number: 11/159,134
- Filed: 2005-06-23
- Published: 2006-01-05
- Granted: 2008-08-05
- Earliest claimed: 2004-07-01
- Assignees: Matsushita Electric Industrial Co., Ltd.
- Inventors: Hisao Ichijo; Hiroyoshi Ogura; Yoshinobu Sato; Teruhisa Ikuta
- Web page: https://patentgrep.com/patent/US7408234B2

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 30/6717: {the source and the drain regions being asymmetrical}
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An object of the present invention is to provide a semiconductor device that is able to realize a low on-resistance maintaining a high drain-to-source breakdown voltage, and a method for manufacturing thereof, the present invention including: a supporting substrate; a semiconductor layer having a P− type active region that is formed on the supporting substrate, interposing a buried oxide film between the semiconductor layer and the supporting substrate; and a gate electrode that is formed on the semiconductor layer, interposing a gate oxide film and a part of a LOCOS film between the gate electrode and the semiconductor layer, wherein the P− type active region has: an N+ type source region; a P type body region; a P+ type back gate contact region; an N type drain offset region; an N+ type drain contact region; and an N type drain buffer region that is formed in a limited region between the N type drain offset region and the P type body region, and the N type drain buffer region is in contact with a source side end of the LOCOS film and is shallower than the N type drain offset region.

## Claims

### Claim 1

A semiconductor device that is a MOS transistor, said semiconductor device comprising:
a semiconductor substrate;
a semiconductor layer of a first conductivity type formed above said semiconductor substrate; and
a gate electrode formed above said semiconductor layer such that a gate insulating film is placed between said gate electrode and said semiconductor layer, wherein said semiconductor layer has:
a body region of the first conductivity type;
a source region of a second conductivity type formed in said body region to be exposed at a surface of said semiconductor layer;
a drain offset region of the second conductivity type;
a drain contact region of the second conductivity type formed in said drain offset region to be exposed at the surface of said semiconductor layer; and
a drain buffer region of the second conductivity type formed between said drain offset region and said body region to adjoin said drain offset region and said body region,
wherein said gate insulating film includes:
a thin film part positioned at a side of said source region; and
a thick film part positioned at a side of said drain contact region and having an end connected to said thin film part, and
wherein said drain buffer region is in contact with said end of said thick film part and has a depth that is less than a depth of said drain offset region; and
wherein said semiconductor layer further has an impurity region of the first conductivity type that is formed immediately under said drain buffer region.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein said impurity region has a section that is overlapped with said body region.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the depth of said drain buffer region is in a range of one-third to one-half of the depth of said drain offset region.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein an impurity concentration of said drain buffer region is lower than an impurity concentration of said drain offset region.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, further comprising an element isolation region, wherein said semiconductor layer is formed above said semiconductor substrate such that a buried insulating film is placed between said semiconductor layer and said semiconductor substrate.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein said thick film part of said gate insulating film is formed by a local-oxidation-of-silicon method.

### Claim 7

A semiconductor device that is a MOS transistor, said semiconductor device comprising:
a semiconductor substrate;
a semiconductor layer of a first conductivity type formed above said semiconductor substrate; and
a gate electrode formed above said semiconductor layer such that a gate insulating film is placed between said gate electrode and said semiconductor layer,
wherein said semiconductor layer has:
a body region of the first conductivity type;
a source region of a second conductivity type formed in said body region to be exposed at a surface of said semiconductor layer;
a drain offset region of the second conductivity type;
a drain contact region of the second conductivity type formed in said drain offset region to be exposed at the surface of said semiconductor layer;
a drain buffer region of the second conductivity type formed between said drain offset region and said body region to adjoin said drain offset region and said body region, and
an impurity region of the first conductivity type formed immediately under said drain buffer region;
wherein said gate insulating film includes:
a thin film part positioned at a side of said source region; and
a thick film part positioned at a side of said drain contact region and having a tapered section with an end connected to said thin film part, and
wherein said drain buffer region is in contact with said end of said thick film part so as to cover a bottom of said tapered section, and has a depth that is less than a depth of said drain offset region; and
wherein said drain offset region is in contact with a bottom of said thick film part so as to cover said bottom.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein said impurity region has a section that is overlapped with said body region.

### Claim 9 (depends on 7)

The semiconductor device according to claim 7, wherein the depth of said drain buffer region is in a range of one-third to one-half of the depth of said drain offset region.

### Claim 10 (depends on 7)

The semiconductor device according to claim 7, wherein an impurity concentration of said drain buffer region is lower than an impurity concentration of said drain offset region.

### Claim 11 (depends on 7)

The semiconductor device according to claim 7, further comprising an element isolation region, wherein said semiconductor layer is formed above said semiconductor substrate such that a buried insulating film is placed between said semiconductor layer and said semiconductor substrate.

### Claim 12 (depends on 7)

The semiconductor device according to claim 7, wherein said thick film part of said gate insulating film is formed by a local-oxidation-of-silicon method.