# US 7,408,228 B2 · Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of floating offset voltage

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- Number: US 7,408,228 B2
- Document ID: US7408228B2
- Status: Granted
- Kind: B2
- Application number: 11/623,806
- Filed: 2007-01-17
- Published: 2007-05-24
- Granted: 2008-08-05
- Earliest claimed: 2003-03-27
- Assignees: Mitsubishi Denki Kabushiki Kaisha
- Inventors: Kazunari Hatade; Hajime Akiyama; Kazuhiro Shimizu
- Web page: https://patentgrep.com/patent/US7408228B2

## CPC

- H10W 10/30: Isolation regions comprising PN junctions
- H10D 84/854: {comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention}
- H10W 10/031: {of isolation regions comprising PN junctions}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p+-type impurity region (33) is formed between an NMOS (14) and a PMOS (15) and in contact with a p-type well (29). An electrode (41) resides on the p+-type impurity region (33) and the electrode (41) is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region (33) has a higher impurity concentration than the p-type well (29) and is shallower than the p-type well (29). Between the p+-type impurity region (33) and the PMOS (15), an n+-type impurity region (32) is formed in the upper surface of the n-type impurity region (28). An electrode (40) resides on the n+-type impurity region (32) and the electrode (40) is connected to a high-voltage-side floating supply absolute voltage (VB).

## Claims

### Claim 1

A semiconductor device for driving a switching device having a first electrode, a second electrode, and a control electrode, said semiconductor device comprising:
a first terminal connected to said first electrode;
a second terminal connected to said first electrode through a capacitive element;
a semiconductor substrate having a first conductivity type;
a first impurity region formed in a main surface of said semiconductor substrate and having a second conductivity type;
a second impurity region formed in a main surface of said first impurity region and having said first conductivity type;
a first transistor having a source/drain region of said second conductivity type, said source/drain region of said first transistor being formed in a main surface of said second impurity region and connected to said first terminal;
a second transistor having a source/drain region of said first conductivity type, said source/drain region of said second transistor being formed in the main surface of said first impurity region and connected to said second terminal; and
at least one of a combination of a third impurity region formed in said main surface of said second impurity region, having said first conductivity type, and connected to said first terminal and a fourth impurity region formed in said main surface of said second impurity region and in contact with said third impurity region, having said second conductivity type, and connected to said first terminal, and a combination of a fifth impurity region formed in said main surface of said first impurity region, having said second conductivity type, and connected to said second terminal and a sixth impurity region formed in said main surface of said first impurity region and in contact with said fifth impurity region, having said first conductivity type, and connected to said second terminal.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, further comprising an isolation region having said first conductivity type and formed in said main surface of said semiconductor substrate and in contact with said first impurity region,
wherein said third and fourth impurity regions are formed between said isolation region and said second impurity region and surround said second impurity region continuously or intermittently.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, further comprising an isolation region having said first conductivity type and formed in said main surface of said semiconductor substrate and in contact with said first impurity region,
wherein said fifth and sixth impurity regions are formed between said isolation region and said second impurity region and surround said second impurity region continuously or intermittently.