# US 7,408,222 B2 · Charge trapping device and method of producing the charge trapping device

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- Number: US 7,408,222 B2
- Document ID: US7408222B2
- Status: Granted
- Kind: B2
- Application number: 11/390,997
- Filed: 2006-03-27
- Published: 2007-09-27
- Granted: 2008-08-05
- Earliest claimed: 2006-03-27
- Assignees: Infineon Technologies AG
- Inventors: Rainer Hagenbeck; Christoph Ludwig; Mark Isler; Elard Stein von Kamienski
- Web page: https://patentgrep.com/patent/US7408222B2

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10B 43/30: characterised by the memory core region
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A charge-trapping device includes a field effect transistor, which has source and drain regions. The source and drain regions have a dopant concentration profile, which has a gradient each in a vertical and a lateral direction with respect to a surface of a semiconductor substrate. The gradient in the lateral direction towards a depletion region of the transistor is larger than the gradient in the vertical direction towards a well region.

## Claims

### Claim 1

A semiconductor device comprising a field effect transistor formed on a semiconductor substrate, the semiconductor device comprising:
a gate dielectric layer formed over a surface portion of the semiconductor substrate;
a gate conductor, in contact with the gate dielectric layer, the gate conductor forming or being electrically connected to a word line; and
a source and a drain region formed within the semiconductor substrate adjacent to the surface portion covered by the gate dielectric layer,
wherein the source and drain region each comprise at least one implant region;
wherein the at least one implant region has a first concentration profile of dopants in a vertical direction with respect to a substrate surface and a second concentration profile of dopants in a lateral direction with respect to the substrate surface; and
wherein the second concentration profile in the lateral direction has a gradient, which is larger than a gradient of the first concentration profile in the vertical direction.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the gate dielectric layer comprises a sequence of layers including a memory layer that is confined on both its top and bottom sides by at least one confinement layer.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein the memory layer comprises a nitride.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, wherein the confinement layers each comprise an oxide.

### Claim 5 (depends on 3)

The semiconductor device according to claim 3, wherein the memory layer is provided to store at least two bits of information independently from each other by means of trapping hot charge carriers generated at a selected pn-junction of the source or drain regions.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the at least one implant region comprises dopants of a first conductivity type, the device further comprising a well region that comprises dopants of a second conductivity type, which is different from the first conductivity type.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein the first conductivity type is n-conductive, and the dopants of the at least one implant region comprise an element selected from the group consisting of Antimony (Sb), Phosphorous (P), and Arsenic (As), and combinations thereof.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein and the source drain regions each comprise at least two implant regions that overlap each other.

### Claim 9

A semiconductor device comprising a field effect transistor formed on a semiconductor substrate, comprising:
a gate dielectric layer formed over a surface portion of the semiconductor substrate;
a gate conductor, in contact with the gate dielectric layer, the gate conductor forming or being electrically connected to a word line; and
a source and a drain region formed within the semiconductor substrate adjacent to the surface portion covered by the gate dielectric layer;
wherein the source and drain region each comprise at least two implant regions overlapping each other;
wherein a concentration of dopants and a lateral dimension of a highly doped one of the overlapping implant regions is larger than that of a lightly doped one of the implant regions; and
wherein a vertical dimension of the highly doped implant region is smaller than that of the lightly doped implant region, such that a pn-junction of the source or drain regions having a strong gradient of dopant concentration extends laterally towards a depletion region of the transistor and a respective pn-junction having a weak gradient of dopant concentration extends vertically towards a well region.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9, wherein the gate dielectric layer comprises a sequence of layers including a memory layer that is confined on its top and bottom side each by at least one confinement layer.

### Claim 11 (depends on 10)

The semiconductor device according to claim 10, wherein the memory layer comprises a nitride.

### Claim 12 (depends on 11)

The semiconductor device according to claim 11, wherein the confinement layers each comprise an oxide.

### Claim 13 (depends on 11)

The semiconductor device according to claim 11, wherein the memory layer is provided to store at least two bits of information independently from each other by means of trapping hot charge carriers generated at a selected one of the pn-junctions of the source or drain regions.

### Claim 14 (depends on 9)

The semiconductor device according to claim 9, wherein the at least two implant regions each comprise dopants of a first conductivity type, and the well region comprises dopants of a second conductivity type, which is different from the first conductivity type.

### Claim 15 (depends on 14)

The semiconductor device according to claim 14, wherein the well region comprises a pocket implantation adjacent to a respective pn-junction of each of the source and drain regions, the pocket implantation zone comprising a concentration of dopants of the second conductivity type.

### Claim 16 (depends on 15)

The semiconductor device according to claim 15, wherein the dopants of the pocket implantation zone comprise boron.

### Claim 17 (depends on 9)

The semiconductor device according to claim 9, wherein the first conductivity type is n-conductive, and the dopants of the highly doped implant region and of the lightly doped implant region comprise the same element, which is selected from the group consisting of Antimony (Sb), Phosphorous (P), and Arsenic (As).

### Claim 18 (depends on 9)

The semiconductor device according to claim 9, wherein the first conductivity type is n-conductive, and the dopants of the highly doped implant region and of the lightly doped implant region comprise different elements, the elements selected from the group consisting of Antimony (Sb), Phosphorous (P), and Arsenic (As).

### Claim 19

A method of producing a semiconductor device, the method comprising:
providing a semiconductor substrate having a surface portion covered by a gate dielectric layer for trapping charges and a stack including a gate electrode formed on the gate dielectric layer; and
performing an implant step with dopants with respect to the semiconductor substrate adjacent to the surface portion covered by the gate dielectric layer, to form source and drain regions, which each include an implant region that has a dopant concentration profile, such that a pn-junction with a strong gradient of dopant concentration extends laterally towards a depletion region of the transistor and a pn-junction with a weak gradient of dopant concentration extends vertically towards a well region.

### Claim 20 (depends on 19)

The method according to claim 19, wherein the implant step is performed by:
depositing a scattering layer on a surface of the semiconductor substrate; and
implanting the dopants into the substrate through the scattering layer such that a channeling tail of the dopant concentration profile occurs in the vertical direction.

### Claim 21 (depends on 19)

The method according to claim 19, wherein the dopants of the implant step are selected to form implant regions of the same first conductivity type.

### Claim 22 (depends on 19)

The method according to claim 19, wherein the gate dielectric layer is formed with a sequence of layers comprising a memory layer which is confined on its top and bottom side each by at least one confinement layer.

### Claim 23 (depends on 22)

The method according to claim 22, wherein the memory layer is formed with a nitride.

### Claim 24 (depends on 22)

The method according to claim 22, wherein the confinement layers are formed with an oxide.

### Claim 25 (depends on 22)

The method according to claim 22, wherein the memory layer is provided to store at least two bits of information independently from each other by means of trapping hot charge carriers generated at a selected pn-junction of the source or drain regions, which has a strong gradient of charge carrier concentration.

### Claim 26 (depends on 19)

The method according to claim 19, further comprising an implant step performed on the semiconductor substrate prior to forming the gate dielectric layer and the stack including the gate conductor in order to form the well region, which comprises dopants of a second conductivity type, which is different from the first conductivity type.

### Claim 27 (depends on 19)

The method according to claim 19, wherein the dopants selected for the implant step comprise a dopant selected from the group consisting of Antimony (Sb), Phosphorous (P), and Arsenic (As).

### Claim 28

A method of producing a semiconductor device, the method comprising:
providing a semiconductor substrate having a surface portion covered by a gate dielectric layer for trapping charges and a stack including a gate electrode formed on the gate dielectric layer;
performing a first implant step with dopants with respect to the semiconductor substrate adjacent to the surface portion covered by the gate dielectric layer, to form source and drain regions, which include a highly doped implant region that has a dopant concentration, a lateral and a vertical dimension;
forming spacers at sidewalls of the stack including the gate electrode in order to cover a surface portion of highly doped implant region; and
thereafter performing a second implant step with dopants with respect to the semiconductor substrate adjacent to the surface portion covered by the additional spacers, to form source and drain regions, which further include a lightly doped implant region, which has a dopant concentration and a lateral dimension smaller than that of the highly doped implant region, a vertical dimension larger than that of the highly doped implant region, such that a pn-junction with a strong gradient of dopant concentration extends laterally towards a depletion region of the transistor and a pn-j unction with a weak gradient of dopant concentration extends vertically towards a well region.

### Claim 29 (depends on 28)

The method according to claim 28, wherein the dopants of the first and second implant step are selected to form implant regions of the same first conductivity type.

### Claim 30 (depends on 28)

The method according to claim 28, wherein the gate dielectric layer is formed with a sequence of layers comprising a memory layer which is confined on its top and bottom side each by at least one confinement layer.

### Claim 31 (depends on 30)

The method according to claim 30, wherein the memory layer is formed with a nitride.

### Claim 32 (depends on 31)

The method according to claim 31, wherein the confinement layers are each formed with an oxide.

### Claim 33 (depends on 31)

The method according to claim 31, wherein the memory layer is provided to store at least two bits of information independently from each other by means of trapping hot charge carriers generated at a selected one of the pn-junctions of the source or drain regions, which has a strong gradient of charge carrier concentration.

### Claim 34 (depends on 28)

The method according to claim 28, further comprising an implant step performed on the semiconductor substrate prior to forming the gate dielectric layer and the stack including the gate conductor in order to form the well region, which comprises dopants of a second conductivity type, which is different from the first conductivity type.

### Claim 35 (depends on 28)

The method according to claim 28, wherein the dopants selected for the first implant step and the dopants selected for the second implant step comprise the same element selected from the group consisting of Antimony (Sb), Phosphorous (P), and Arsenic (As).

### Claim 36 (depends on 28)

The method according to claim 28, wherein the dopants selected for the first implant step and the dopants selected for the second implant step comprise different elements that are selected from the group consisting of Antimony (Sb), Phosphorous (P), and Arsenic (As).

### Claim 37 (depends on 34)

The method according to claim 34, wherein the step of forming the well region comprises forming a pocket implantation region adjacent to a respective pn-junction each of the source and drain regions, the pocket implantation zone comprising a concentration of dopants of the second conductivity type.

### Claim 38 (depends on 37)

The method according to claim 37, wherein the dopants of the pocket implantation zone are selected to comprise boron.

### Claim 39

Method of producing a semiconductor device, the method comprising
providing a semiconductor substrate having a surface portion covered by a gate dielectric layer for trapping charges and a stack including a gate electrode formed on the gate dielectric layer;
performing a first implant step with dopants with respect to the semiconductor substrate adjacent to the surface portion covered by the gate dielectric layer, to form source and drain regions, which include a highly doped implant region that has a dopant concentration, a lateral and a vertical dimension;
applying a thermal diffusion process to increase the lateral dimension of the highly doped implant region;
thereafter performing a second implant step with dopants with respect to the semiconductor substrate adjacent to the surface portion covered by the additional spacers, to form source and drain regions, which further include a lightly doped implant region, which has a dopant concentration and a lateral dimension smaller than that of the highly doped implant region, a vertical dimension larger than that of the highly doped implant region, such that a pn-junction with a strong gradient of dopant concentration extends laterally towards a depletion region of the transistor and a pn-j unction with a weak gradient of dopant concentration extends vertically towards a well region.

### Claim 40 (depends on 39)

The method according to claim 39, wherein the dopants of the first and second implant step are selected to form implant regions of the same first conductivity type.

### Claim 41 (depends on 39)

The method according to claim 39, wherein the gate dielectric layer is formed with a sequence of layers comprising a memory layer which is confined on its top and bottom side each by at least one confinement layer.

### Claim 42 (depends on 41)

The method according to claim 41, wherein the memory layer is formed with a nitride.

### Claim 43 (depends on 42)

The method according to claim 42, wherein the confinement layers are each formed from an oxide.

### Claim 44 (depends on 42)

The method according to claim 42, wherein the memory layer is provided to store at least two bits of information independently from each other by means of trapping hot charge carriers generated at a selected one of the pn-junctions of the source or drain regions, which has a strong gradient of charge carrier concentration.

### Claim 45 (depends on 39)

The method according to claim 39, further comprising an implant step performed on the semiconductor substrate prior to forming the gate dielectric layer and the stack including the gate conductor in order to form the well region, which comprises dopants of a second conductivity type, which is different from the first conductivity type.

### Claim 46 (depends on 39)

The method according to claim 39, wherein the dopants selected for the first implant step and the dopants selected for the second implant step comprise the same element, the element being selected from the group consisting of Antimony (Sb), Phosphorous (P), and Arsenic (As).

### Claim 47 (depends on 39)

The method according to claim 39, wherein the dopants selected for the first implant step and the dopants selected for the second implant step comprise different elements that are selected from the group consisting of Antimony (Sb), Phosphorous (P), and Arsenic (As).

### Claim 48 (depends on 44)

The method according to claim 44, wherein the step of forming the well region comprises forming a pocket implantation region adjacent to a respective pn-junction each of the source and drain regions, the pocket implantation zone comprising a concentration of dopants of the second conductivity type.

### Claim 49 (depends on 48)

The method according to claim 48, wherein the dopants of the pocket implantation zone are selected to comprise boron.