# US 7,408,219 B2 · Nonvolatile semiconductor memory device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,408,219 B2
- Document ID: US7408219B2
- Status: Granted
- Kind: B2
- Application number: 11/099,658
- Filed: 2005-04-06
- Published: 2006-01-12
- Granted: 2008-08-05
- Earliest claimed: 2004-07-12
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Tea-kwang Yu; Weon-ho Park; Kyoung-hwan Kim; Kwang-tae Kim
- Web page: https://patentgrep.com/patent/US7408219B2

## CPC

- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10B 41/30: characterised by the memory core region
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

In a nonvolatile semiconductor memory device, and a method of fabricating the same, the nonvolatile semiconductor memory device includes a cell doping region and source/drain regions in a semiconductor substrate, the cell doping region being doped as a first conductive type, a channel region disposed between the source/drain regions in the semiconductor substrate, a tunnel doping region of the first conductive type formed in a predetermined region of an upper portion of the cell doping region, the tunnel doping region being doped in a higher concentration than that of the cell doping region, a tunnel insulating layer formed on a surface of the semiconductor substrate on the tunnel doping region, a gate insulating layer surrounding the tunnel insulating layer and covering the channel region and the cell doping region exposed beyond the tunnel doping region, and a gate electrode covering the tunnel insulating layer and on the gate insulating layer.

## Claims

### Claim 1

A nonvolatile semiconductor memory device, comprising:
a cell doping region and source/drain regions in a semiconductor substrate, the cell doping region being doped as a first conductive type;
a channel region disposed between the source/drain regions in the semiconductor substrate;
a tunnel doping region of the first conductive type formed in a predetermined region of an upper portion of the cell doping region, the tunnel doping region being doped in a higher concentration than that of the cell doping region, a width of the tunnel doping region being smaller than a width of the cell doping region;
a tunnel insulating layer formed on a surface of the semiconductor substrate on the tunnel doping region, a width of the tunnel insulating layer being smaller than the width of the tunnel doping region;
a gate insulating layer surrounding the tunnel insulating layer and covering the channel region and the cell doping region exposed beyond the tunnel doping region; and
a gate electrode covering the tunnel insulating layer and on the gate insulating layer.

### Claim 2 (depends on 1)

The memory device as claimed in claim 1, wherein the first conductive material is an n-type impurity.

### Claim 3 (depends on 1)

The memory device as claimed in claim 1, wherein a doping concentration of the tunnel doping region depends at least in part on a distance between end portions of the tunnel insulating layer and the cell doping region.

### Claim 4 (depends on 1)

The memory device as claimed in claim 1, wherein the width of the tunnel insulating layer is between about 0.15 to about 0.3 μm and a thickness of the tunnel insulating layer is between about 70 to about 120 Å.

### Claim 5 (depends on 1)

The memory device as claimed in claim 1, wherein a sidewall of the tunnel insulating layer has a vertical profile.

### Claim 6 (depends on 1)

The memory device as claimed in claim 1, wherein the cell doping region is doped with an ion selected from the group consisting of arsenic (As) ion and phosphorous (P) ions.

### Claim 7 (depends on 1)

The memory device as claimed in claim 1, further comprising a selection transistor in the semiconductor substrate.

### Claim 8 (depends on 7)

The memory device as claimed in claim 7, wherein the high concentration doping region is formed at least partially under the selection transistor.

### Claim 9 (depends on 1)

The memory device as claimed in claim 1, wherein the width of the tunnel doping region and the width of the cell doping region are measured in a channel length direction of the channel region.

### Claim 10 (depends on 1)

The memory device as claimed in claim 1, wherein the cell doping region completely surrounds the tunnel doping region.