# US 7,408,215 B2 · Dynamic random access memory

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- Number: US 7,408,215 B2
- Document ID: US7408215B2
- Status: Granted
- Kind: B2
- Application number: 11/696,160
- Filed: 2007-04-03
- Published: 2008-02-07
- Granted: 2008-08-05
- Earliest claimed: 2006-08-02
- Assignees: Nanya Technology Corporation
- Inventors: Ming-Cheng Chang; Neng-Tai Shih
- Web page: https://patentgrep.com/patent/US7408215B2

## CPC

- H10B 12/395: {the transistor being vertical}
- H10B 12/0387: {Making the trench}
- H10D 89/10: Integrated device layouts
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A DRAM structure on a silicon substrate has an active area, gate conductors, deep trench capacitors, and vertical transistors. The deep trench capacitors are formed at intersections of the active area and the gate conductors, and each deep trench capacitor is coupled electrically to the corresponding vertical transistor to form a memory cell. The transistor includes a gate, a source in a lateral side of the gate, and a drain in another lateral side of the gate The depth of the drain is different from the depth of the source.

## Claims

### Claim 1

A dynamic random access memory (DRAM) on a silicon substrate, comprising:
at least an active area on the silicon substrate;
a plurality of gate conductors on the silicon substrate;
a plurality of deep trench capacitors, each deep trench capacitor is positioned in the silicon substrate at respective intersections of the plurality of gate conductors and the active area; and
a plurality of vertical transistors in the silicon substrate, each vertical transistor is coupled to each respective deep trench capacitor to form a memory cell, each vertical transistor further comprising:
a gate;
a source in one side of the gate; and
a drain in another side of the gate, a depth of the source is different from a depth of the drain.

### Claim 2 (depends on 1)

The DRAM of claim 1, wherein the DRAM is a checkerboard trench-DRAM.

### Claim 3 (depends on 1)

The DRAM of claim 1, wherein the active area is perpendicular to the gate conductors.

### Claim 4 (depends on 1)

The DRAM of claim 1, wherein each deep trench capacitor comprises a lower electrode, an upper electrode, and a dielectric layer between the upper electrode and the lower electrode.

### Claim 5 (depends on 1)

The DRAM of claim 1, wherein the silicon substrate further comprises a plurality of shallow trench isolations (STI) and single sided buried straps.

### Claim 6 (depends on 5)

The DRAM of claim 5, wherein the silicon substrate further comprises a plurality of gate recesses, and each gate is in each respective gate recess.

### Claim 7 (depends on 6)

The DRAM of claim 6, wherein each transistor further comprises a gate insulating layer between the silicon substrate and the gate.

### Claim 8 (depends on 1)

The DRAM of claim 1, wherein the depth of the drain is deeper than the depth of the source.