# US 7,408,198 B2 · Thin film transistor, thin film transistor array and repairing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,408,198 B2 - Document ID: US7408198B2 - Status: Granted - Kind: B2 - Application number: 11/307,540 - Filed: 2006-02-13 - Published: 2007-08-16 - Granted: 2008-08-05 - Earliest claimed: 2006-02-13 - Assignees: Chunghwa Picture Tubes, Ltd. - Inventors: Wen-Hsiung Liu - Web page: https://patentgrep.com/patent/US7408198B2 ## CPC - H10D 86/60: wherein the TFTs are in active matrices - H10D 86/441: {Interconnections, e.g. scanning lines} - G02F 1/13606: {having means for reducing parasitic capacitance} - G02F 1/13625: {Patterning using multi-mask exposure} - G02F 1/136268: {Switch defects} - H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate} - H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS ## Abstract A thin film transistor (TFT) including a gate, a semiconductor layer, a source and a drain is provided. The gate has a control part, a connection part and a capacitance compensation part. The connection part is disposed between the control part and the capacitance compensation part for joining the two parts together. The semiconductor layer is disposed over the gate, the source and the drain are disposed on the semiconductor layer. An end of the drain overlaps the control part of the gate with a first region for composing a first parasitic capacitance; while another end of the drain overlaps the capacitance compensation part of the gate with a second region for composing a second parasitic capacitance. In a TFT array with the TFT, the sum of the first parasitic capacitance and the second parasitic capacitance is a constant. ## Claims ### Claim 1 A thin film transistor (TFT) comprising: a gate, disposed on a substrate and having a control part, a connection part and a capacitance compensation part, wherein the connection part joins the control part and the capacitance compensation part; a semiconductor layer, disposed over the gate; a source, disposed on a part of the semiconductor layer; and a drain, disposed on a part of the semiconductor layer, wherein a channel is formed between the source and the drain in the semiconductor layer, a first overlapping region between an end of the drain and the control part of the gate and the first overlapping region induces a first parasitic capacitance, a second overlapping region between another end of the drain and the capacitance compensation part of the gate and the second overlapping region induces a second parasitic capacitance, wherein the sum of the first parasitic capacitance and the second parasitic capacitance is a constant. ### Claim 2 (depends on 1) The TFT as recited in claim 1, wherein the sum of the first overlapping region area and the second overlapping region area is a constant. ### Claim 3 (depends on 1) The TFT as recited in claim 1, wherein the control part and the capacitance compensation part of the gate are bar-shaped, respectively. ### Claim 4 (depends on 3) The TFT as recited in claim 3, wherein the control part and the capacitance compensation part of the gate are parallel. ### Claim 5 (depends on 1) The TFT as recited in claim 1, wherein the source further has an extending part and the extending part overlaps with a part of the capacitance compensation part. ### Claim 6 (depends on 1) The TFT as recited in claim 1, wherein the channel extends from above the control part of the gate towards above the connection part of the gate. ### Claim 7 (depends on 1) The TFT as recited in claim 1, wherein the semiconductor layer resides over the control part and the capacitance compensation part of the gate. ### Claim 8 A thin film transistor array (TFT array), comprising: a substrate, having a plurality of pixel regions; a plurality of TFTs, disposed in each corresponding pixel region, respectively, the TFTs comprising: a gate, disposed on the substrate and having a control part, a connection part and a capacitance compensation part, wherein the connection part joins the control part and the capacitance compensation part; a semiconductor layer, disposed over the gate; a source, disposed on a part of the semiconductor layer; and a drain, disposed on a part of the semiconductor layer, wherein a channel is formed between the source and the drain in the semiconductor layer, a first overlapping region between an end of the drain and the control part of the gate and the first overlapping region induces a first parasitic capacitance, a second overlapping region between another end of the drain and the capacitance compensation part of the gate and the second overlapping region induces a second parasitic capacitance, wherein the sum of the first parasitic capacitance and the second parasitic capacitance in each pixel region is a constant; and a plurality of pixel electrodes, disposed in each corresponding pixel region, respectively and electrically connected to the corresponding TFT, respectively. ### Claim 9 (depends on 8) The TFT array as recited in claim 8, wherein in each pixel region, the sum of the first overlapping region area and the second overlapping region area is a constant. ### Claim 10 (depends on 8) The TFT array as recited in claim 8, wherein the control part and the capacitance compensation part of the gate are bar-shaped, respectively. ### Claim 11 (depends on 10) The TFT array as recited in claim 10, wherein the control part and the capacitance compensation part of the gate are parallel. ### Claim 12 (depends on 8) The TFT array as recited in claim 8, wherein the source in each pixel region further has an extending part and the extending part overlaps with a part of the capacitance compensation part. ### Claim 13 (depends on 8) The TFT array as recited in claim 8, wherein the channel extends from above the control part of the gate towards above the connection part of the gate. ### Claim 14 (depends on 8) The TFT array as recited in claim 8, wherein the semiconductor layer resides over the control part and the capacitance compensation part of the gate. ### Claim 15 (depends on 12) A repairing method of a thin film transistor array (TFT array), suitable for repairing the TFT array as recited in claim 12 when an electrostatic damage occurs between the capacitance compensation part of one of the gates and the extending part of the source or the drain, the repair method comprising: cutting off the connection part of the gate, so that the capacitance compensation part of the gate and the connection part of the gate are electrically insulated from each other; and fusing the capacitance compensation part and the drain or the extending part of the source. ### Claim 16 (depends on 15) The repair method of a TFT array as recited in claim 15, wherein the method for cutting off the connection part of the gate comprises a laser cutting process. ### Claim 17 (depends on 15) The repair method of a TFT array as recited in claim 15, wherein the method for fusing the capacitance compensation part and the drain or the extending part of the source comprises a laser fusing process.