# US 7,407,890 B2 · Patterning sub-lithographic features with variable widths

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- Number: US 7,407,890 B2
- Document ID: US7407890B2
- Status: Granted
- Kind: B2
- Application number: 11/379,634
- Filed: 2006-04-21
- Published: 2007-10-25
- Granted: 2008-08-05
- Earliest claimed: 2006-04-21
- Assignees: International Business Machines Corporation
- Inventors: Haining S. Yang
- Web page: https://patentgrep.com/patent/US7407890B2

## CPC

- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10B 10/00: Static random access memory [SRAM] devices
- H10B 10/12: {comprising a MOSFET load element}
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 89/10: Integrated device layouts
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 50/696: {Process specially adapted to improve the resolution of the mask}
- H10P 76/408: {characterised by their sizes, orientations, dispositions, behaviours or shapes}
- H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- Y10S 438/942: Masking
- Y10S 438/947: Subphotolithographic processing
- Y10S 977/887: Nanoimprint lithography, i.e. nanostamp
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A method of processing a substrate of a device comprises the as following steps. Form a cap layer over the substrate. Form a dummy layer over the cap layer, the cap layer having a top surface. Etch the dummy layer forming patterned dummy elements of variable widths and exposing sidewalls of the dummy elements and portions of the top surface of the cap layer aside from the dummy elements. Deposit a spacer layer over the device covering the patterned dummy elements and exposed surfaces of the cap layer. Etch back the spacer layer forming sidewall spacers aside from the sidewalls of the patterned dummy elements spaced above a minimum spacing and forming super-wide spacers between sidewalls of the patterned dummy elements spaced less than the minimum spacing. Strip the patterned dummy elements. Expose portions of the substrate aside from the sidewall spacers. Pattern exposed portions of the substrate by etching into the substrate.

## Claims

### Claim 1

A method of processing a substrate of a device comprising the steps as follows:
forming a cap layer having a top surface over said substrate;
forming a dummy layer over said top surface of said cap layer;
patterning dummy elements with patterns of variable widths and exposing sidewalls of said dummy elements and portions of said top surface of said cap layer aside from said dummy elements;
forming spacers including sidewall spacers aside from said sidewalls of said patterned dummy elements spaced above a minimum spacing on sidewalls of widely spaced dummy elements and forming super-wide spacers between sidewalls of said patterned dummy elements spaced less than said minimum spacing filling spaces between closer dummy elements;
stripping said patterned dummy elements;
exposing portions of said substrate aside from said spacers; and
patterning exposed portions of said substrate by etching into said substrate.

### Claim 2 (depends on 1)

The method of claim 1, including forming a patterning mask with patterned openings of variable widths therethrough over said dummy layer prior to patterning thereof.

### Claim 3 (depends on 1)

The method of claim 1 wherein said dummy layer comprises a blanket layer of polysilicon.

### Claim 4 (depends on 1)

The method of claim 1 wherein said cap layer comprises a blanket layer of silicon nitride.

### Claim 5 (depends on 1)

The method of claim 1 wherein said spacer layer comprises a hard mask material.

### Claim 6 (depends on 1)

The method of claim 1, wherein said spacer layer is composed of silicon oxide.

### Claim 7 (depends on 1)

The method of claim 1, wherein said dummy layer is deposited as a conformal layer forming a dummy mask layer composed of polysilicon.

### Claim 8 (depends on 7)

The method of claim 7 including patterning said dummy mask layer is patterned by RIE.

### Claim 9 (depends on 1)

The method of claim 1 wherein etching into said substrate is performed by RIE.

### Claim 10 (depends on 1)

The method of claim 1 including the steps as follows:
forming said cap layer into a patterned cap layer using said spacers as a hard mask;
then etching into said substrate by RIE using said cap layer as a mask to form isolation trenches;
then depositing isolation dielectric layer over said device overfilling said isolation trenches;
planarizing said isolation dielectric; and
stripping said cap layer.

### Claim 11

A method of processing a substrate of a device comprising the steps as follows:
forming a cap layer on said substrate of said device with said cap layer having a top surface;
forming a dummy layer over said top surface of said cap layer;
forming a patterning mask with patterned openings of variable widths therethrough over said dummy layer;
performing an etch through said patterned openings extending through said dummy layer forming patterned dummy elements of variable widths and exposing sidewalls of said dummy elements and portions of said top surface of said cap layer aside from said dummy elements;
stripping said patterning mask exposing top surfaces of said patterned dummy layer;
depositing a conformal spacer layer over said device covering said patterned dummy elements and exposed surfaces of said cap layer;
forming a secondary pattern of sublithographic width patterns by etching back said conformal spacer layer forming spacers including sidewall spacers aside from said sidewalls of said patterned dummy elements spaced above a minimum spacing on sidewalls of widely spaced dummy elements and forming super-wide spacers between sidewalls of said patterned dummy elements spaced less than said minimum spacing filling spaces between closer dummy elements;
stripping said patterned dummy elements;
forming said cap layer into a patterned cap layer using said spacers as a hard mask; and
patterning said substrate with said patterned cap layer by etching recesses into said substrate.

### Claim 12 (depends on 11)

The method of claim 11, including forming a patterning mask with patterned openings of variable widths therethrough over said dummy layer prior to etching thereof.

### Claim 13 (depends on 11)

The method of claim 11 wherein said dummy layer comprises a blanket layer of polysilicon.

### Claim 14 (depends on 11)

The method of claim 11 wherein said cap layer comprises a blanket layer of silicon nitride.

### Claim 15 (depends on 11)

The method of claim 11 wherein said spacer layer comprises a hard mask material.

### Claim 16 (depends on 11)

The method of claim 11, wherein said spacer layer is composed of silicon oxide.

### Claim 17 (depends on 11)

The method of claim 11 including depositing said dummy layer as a blanket layer of polysilicon.

### Claim 18 (depends on 11)

The method of claim 11 including patterning said substrate by etching into said substrate by RIE.

### Claim 19 (depends on 11)

The method of claim 11 including filling said trenches in said substrate with dielectric material to form Shallow Trench Isolation (STI) regions with said dielectric material in said trenches.

### Claim 20 (depends on 19)

The method of claim 19 including:
depositing said dielectric material by High Density Plasma (HDP) deposition of silicon oxide covering said device; and
then planarizing said dielectric material to form said STI regions.

### Claim 21 (depends on 17)

The method of claim 17 including patterning said dummy mask layer by RIE.

### Claim 22 (depends on 11)

The method of claim 11 including forming said cap layer into a patterned cap layer using said spacers as a hard mask and then etching said substrate by RIE using said cap layer as a mask.