# US 7,407,879 B2 · Chemical planarization performance for copper/low-k interconnect structures

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- Number: US 7,407,879 B2
- Document ID: US7407879B2
- Status: Granted
- Kind: B2
- Application number: 11/369,476
- Filed: 2006-03-07
- Published: 2006-07-27
- Granted: 2008-08-05
- Earliest claimed: 2003-07-28
- Assignees: International Business Machines Corporation
- Inventors: Lee M Nicholson; Wei-Tsu Tseng; Christy S Tyberg
- Web page: https://patentgrep.com/patent/US7407879B2

## CPC

- H10W 20/48: Insulating materials thereof
- H10W 20/058: {by depositing on sacrificial masks, e.g. using lift-off}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/097: {by thermally treating}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W 20/084: {for dual-damascene structures}
- Y10T 428/31663: As siloxane, silicone or silane
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.

## Claims

### Claim 1

A method of forming an electrical interconnect structure on a substrate, comprising:
forming a low k CMP protective layer on a first low-k dielectric or an ultra low k dielectric layer disposed on a substrate such that said CMP protective layer covalently bonds with said first low-k dielectric or said ultra low k dielectric layer; and
forming a hardmask/CMP polish stop layer on said low k CMP protective layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein said first low-k dielectric layer is a first spin-on low k dielectric layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein said spin-on low k dielectric layer is selected from the group consisting of: SiLK™, GX-3™, porous SiLK™, GX-3p™, JSR LKD 5109™, porous spin-on SiwCxOyHz material, spin-on dielectric material, low k spin-on dielectric material and porous low k spin-on dielectric material.

### Claim 4 (depends on 1)

The method of claim 1, wherein said first low-k dielectric layer is porous.

### Claim 5 (depends on 1)

The method of claim 1, wherein said first low-k dielectric layer has a thickness from about 600 Å to about 8000 Å.

### Claim 6 (depends on 1)

The method of claim 1, wherein said low-k CMP protective layer is a spin-on low-k CMP protective layer having a thickness from about 50 Å to about 500 Å.

### Claim 7 (depends on 1)

The method of claim 1, wherein said CMP protective layer is comprised of a spin-on material selected from the group consisting of: HOSP™, AP 6000™, HOSP BESt™, Ensemble™ Etch Stop, Ensemble™ Hard Mask, organo silsesquioxane, hydrido silsesquioxane, hydrido-organo silsesquioxane copolymer, siloxane and silsesquioxane.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
forming a metal line in said first low-k dielectric layer.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
forming a metal via in said first low-k dielectric layer.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
adding additional dielectric layers; and
adding conductors to complete said electrical interconnect structure.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
forming a stack of dielectric layers on said substrate, including at least said first low-k dielectric layer and said low k CMP protective layer; and
forming a plurality of patterned metal conductors within said dielectric layers.

### Claim 12 (depends on 11)

The method of claim 11 further comprising:
curing said dielectric layers to promote crosslinking of said CMP protective layer to said first low k dielectric layer and to reduce CMP polish rate of said CMP protective layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein said first low-k dielectric and said CMP protective layers are cured in a single step.

### Claim 14 (depends on 13)

The method of claim 13, wherein said first low-k dielectric and said CMP protective layers are cured in a furnace at a temperature from about 300° C. to about 500° C. within a period of time from about 15 minutes to about 3 hours.

### Claim 15 (depends on 12)

The method of claim 12, wherein said dielectric layers in said stack are cured after sequential application in a single tool.

### Claim 16 (depends on 15)

The method of claim 15, wherein said application tool is a spin coating tool containing high temperature hot plate baking chambers.

### Claim 17 (depends on 1)

The method of claim 1, wherein said first low k dielectric layer is a spin-on first low k dielectric layer and said low k CMP protective layer is a spin-on low k CMP protective layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein said spin-on low k CMP protective layer has fine and evenly dispersed pores.

### Claim 19 (depends on 1)

The method of claim 1, wherein said hardmask/CMP polish stop layer is a conventional CVD hardmask/CMP polish stop layer.