# US 7,407,857 B2 · Method of making a scalable flash EEPROM memory cell with notched floating gate and graded source region

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- Number: US 7,407,857 B2
- Document ID: US7407857B2
- Status: Granted
- Kind: B2
- Application number: 11/338,070
- Filed: 2006-01-23
- Published: 2006-06-08
- Granted: 2008-08-05
- Earliest claimed: 2003-07-02
- Assignees: Integrated Memory Technologies, Inc.
- Inventors: Ching-Shi Jeno; Ting P. Yen
- Web page: https://patentgrep.com/patent/US7407857B2

## CPC

- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10B 41/30: characterised by the memory core region
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/685: {from the channel}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- G11C 16/0458: {comprising two or more independent floating gates which store independent data}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An memory device, and method of making same, that includes source and drain regions defining a channel region therebetween. A select gate is formed over and insulated from a first portion of the channel region. A conductive floating gate is disposed over and insulated from the source region and a second portion of the channel region. A notch is formed in the floating gate bottom surface having an edge that is either aligned with an edge of the source region or is disposed over the source region. A conductive control gate is disposed adjacent to the floating gate. By having the source region terminate under the thicker insulation region provided by the notch, the breakdown voltage of the source junction is increased. Alternately, the lower portion of the floating gate is formed entirely over the source region, for producing fringing fields to control the adjacent portion of the channel region.

## Claims

### Claim 1

A method of making a memory device on a semiconductor substrate of a first conductivity type, comprising:
forming spaced-apart first and second regions in the substrate that have a second conductivity type different from the first conductivity type, wherein a channel region is defined in the substrate between the first and second regions;
forming a conductive select gate over and insulated from a first portion of the channel region;
forming a conductive floating gate having a bottom surface disposed over and insulated from the first region and a second portion of the channel region, wherein the floating gate formation includes forming a notch in the bottom surface at least partially over the channel region second portion and having an edge that is aligned with an edge of the first region or that is disposed over the first region; and
forming a conductive control gate having a first portion disposed adjacent to the floating gate.

### Claim 2

A method of making a memory device on a semiconductor substrate of a first conductivity type, comprising:
forming spaced-apart first and second regions in the substrate that have a second conductivity type different from the first conductivity type, wherein a channel region is defined in the substrate between the first and second regions;
forming a conductive select gate over and insulated from a first portion of the channel region;
forming a conductive floating gate having a bottom surface disposed over and insulated from the first region and a second portion of the channel region, wherein the floating gate formation includes forming a notch in the bottom surface having an edge that is aligned with an edge of the first region or that is disposed over the first region; and
forming a conductive control gate having a first portion disposed adjacent to the floating gate;
wherein the formation of the floating gate includes:
forming insulation material of varying thickness over the substrate; and
forming conductive material over the insulation material.

### Claim 3 (depends on 2)

The method of claim 2, wherein the formation of the floating gate further comprises:
performing an anisotropic etch to remove the conductive material except for a spacer of the conductive material disposed over the insulation material.

### Claim 4 (depends on 2)

The method of claim 2, wherein the insulation material includes a first portion having a thickness greater than that of a second portion of the insulation material, and wherein the floating gate includes:
a first portion disposed over the notch and the insulation material first portion; and
a second portion disposed over the insulation material second portion and not disposed over the notch.

### Claim 5 (depends on 4)

The method of claim 4, wherein the formation of the floating gate includes forming a third portion of the floating gate that extends up and over the select gate.

### Claim 6 (depends on 1)

The method of claim 1 wherein the formation of the control gate includes:
forming the first portion of the control gate laterally adjacent to the floating gate, and
forming a second portion of the control gate that extends up and over the floating gate.

### Claim 7 (depends on 1)

The method of claim 1, wherein:
the formation of the control gate includes forming a second notch in a bottom surface of the control gate; and
the formation of the floating gate includes forming a protrusion on a top surface of the floating gate, wherein the floating gate protrusion faces and is insulated from the second notch.

### Claim 8 (depends on 1)

The method of claim 1, wherein the formation of the notch edge includes forming a portion of the floating gate bottom surface that is generally orthogonal to a surface of the substrate.

### Claim 9 (depends on 2)

The method of claim 2, wherein:
the formation of the insulation material of varying thickness over the substrate includes:
forming a composite spacer of first and second insulation materials over the substrate;
removing the second insulation material leaving the first insulation material disposed over the substrate;
forming a layer of third insulation material over the substrate and adjacent to the first insulation material;
wherein the layer of third insulation material has a thickness that is less than that of the first insulation material, and wherein the floating gate is formed over the third insulation material and the first insulation material.

### Claim 10 (depends on 9)

The method of claim 9, wherein the formation of the composite spacer includes:
forming a layer of the first insulation material over the substrate and along a sidewall of the select gate;
forming a layer of the second insulation material over the layer of the first insulation material; and
performing an anisotropic etch to remove the layers of first and second insulation materials except for a spacer of the first and second insulation materials disposed over the substrate and adjacent the select gate.

### Claim 11

A method of making a memory device on a semiconductor substrate of a first conductivity type, comprising:
forming spaced-apart first and second regions in the substrate that have a second conductivity type different from the first conductivity type, wherein a channel region is defined in the substrate between the first and second regions, and wherein the channel region includes a first portion adjacent the first region and a second portion adjacent the second region;
forming a conductive select gate over and insulated from the channel region second portion for controlling a conductivity of the channel region second portion;
forming a conductive floating gate having a first portion disposed entirely over and insulated from the first region for generating fringing fields that control a conductivity of the channel region first portion, wherein the floating gate first portion including a bottom surface disposed entirely over and insulated from the first region and a side surface extending from the bottom surface and away from the substrate; and
forming a conductive control gate having a first portion disposed adjacent to the floating gate.

### Claim 12 (depends on 11)

The method of claim 11, wherein the side surface is aligned with an edge of the first region.

### Claim 13 (depends on 11)

The method of claim 11, wherein the floating gate includes a second portion that extends up and over the select gate.

### Claim 14 (depends on 13)

The method of claim 13, wherein the formation of the floating gate includes:
forming insulation material over the first region;
forming conductive material over the insulation material;
performing an anisotropic etch to remove the conductive material except for a spacer of the conductive material disposed over the insulation material.

### Claim 15 (depends on 11)

The method of claim 11, wherein the formation of the control gate includes:
forming the first portion of the control gate laterally adjacent to the floating gate, and
forming a second portion of the control gate that extends up and over the floating gate.

### Claim 16 (depends on 11)

The device of claim 11, wherein the floating gate side surface is generally orthogonal to a surface of the substrate.