# US 7,407,852 B2 · Trench capacitor of a DRAM and fabricating method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 7,407,852 B2
- Document ID: US7407852B2
- Status: Granted
- Kind: B2
- Application number: 11/161,760
- Filed: 2005-08-16
- Published: 2007-02-22
- Granted: 2008-08-05
- Earliest claimed: 2005-08-16
- Assignees: United Microelectronics Corp.
- Inventors: Yi-Nan Su; Jun-Chi Huang
- Web page: https://patentgrep.com/patent/US7407852B2

## CPC

- H10D 1/047: {of conductor-insulator-semiconductor capacitors, e.g. trench capacitors}
- H10B 12/0387: {Making the trench}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method of fabricating trench capacitors is described. A substrate having at least one isolation structure is provided. A first trench and a second trench are formed in the substrate beside the isolation structure. A first lower electrode and a second lower electrode are formed in the substrate around the first trench and the second trench. A first capacitor dielectric layer and a second capacitor dielectric layer are formed on the respective surfaces of the first trench and the second trench. A first upper electrode and a second upper electrode are formed to fill the first trench and the second trench. A portion of the isolation structure between the first trench and the second trench is removed to form an opening. A conductive layer is formed to fill the opening and connect electrically with the first upper electrode and the second upper electrode.

## Claims

### Claim 1

A method of fabricating trench capacitors, comprising the steps of:
providing a substrate having at least an isolation structure formed thereon;
forming a first trench and a second trench in the substrate beside the isolation structure and removing a portion of the isolation structure between the first trench and the second trench to form an opening;
forming a first lower electrode and a second lower electrode in the substrate around the first trench and the second trench respectively;
forming a first capacitor dielectric layer and a second capacitor dielectric layer on the respective surfaces of the first trench and the second trench; and
filling the first trench, the second trench and the opening with a conductive material to form a first upper electrode, a second upper electrode and a conductive layer, wherein the first upper electrode and the second upper electrode are electrically connected through the conductive layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein after forming the first upper electrode, the second upper electrode and the conductive layer. tbrther includes forming a contact on the conductive layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein after forming the first upper electrode, the second upper electrode and the conductive layer, further includes forming a first contact and a second contact on the first upper electrode and the second upper electrode respectively.

### Claim 4 (depends on 1)

The method of claim 1, wherein the step of removing a portion of the isolation structure between the first trench and the second wench includes performing an etching operation.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first trench and the second trench penetrate through the isolation structure.

### Claim 6 (depends on 1)

The method of claim 1, wherein the steps for fanning the first lower electrode and the second lower electrode include:
forming a doped insulating layer on the respective surfaces of the first trench and the second trench; and
performing a thermal treatment.

### Claim 7 (depends on 6)

The method of claim 6, wherein the material constituting the doped insulating layer comprises an arsenic-doped silicon oxide layer or a boron-doped silicon oxide layer.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first capacitor dielectric layer and the second capacitor dielectric layer comprise a silicon oxide layer or an oxide/nitride/oxide stack layer.