# US 7,407,845 B2 · Field effect transistor and method for manufacturing the same

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- Number: US 7,407,845 B2
- Document ID: US7407845B2
- Status: Granted
- Kind: B2
- Application number: 11/048,369
- Filed: 2005-01-31
- Published: 2005-08-11
- Granted: 2008-08-05
- Earliest claimed: 2004-02-10
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Choong-Ho Lee; Jae-Man Yoon; Dong-Gun Park; Chul Lee
- Web page: https://patentgrep.com/patent/US7407845B2

## CPC

- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/674: {characterised by the active materials}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6213: {having rounded corners}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

In one embodiment, a semiconductor device includes a semiconductor substrate having a lower layer and an upper layer overlying the lower layer. The upper layer is arranged and structured to form first and second active regions that are spaced apart from each other and protrude from an upper surface of the lower layer. A third active region of a bridge shape is distanced vertically from the upper surface of the lower layer and connects the first and second active regions. The device further includes a gate electrode, which is formed with a gate insulation layer surrounding the third active region, so that the third active region functions as a channel.

## Claims

### Claim 1

A method of manufacturing a field effect transistor (FET), the method comprising:
providing a semiconductor substrate including a lower layer and an upper layer overlying the lower layer, the upper layer a single-crystal silicon layer;
forming first and second active regions from the upper layer, first and second active regions spaced apart from each other and protruding from an upper surface of the lower layer;
forming a third active region of a bridge shape from the upper layer, which is distanced vertically from the upper surface of the lower layer and which connects the first and second active regions; and
forming a gate, insulation layer surrounding the third active region, and forming a gate electrode on the gate insulation layer so that the third active region functions as a channel.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming of the first, second and third active regions comprises:
forming a fin active region protruded from the lower layer;
forming an interlayer dielectric layer on the first and second active regions of both ends of the fin active region;
ion implanting an impurity in a center portion of the fin active region to form a buried impurity region by using the interlayer dielectric layer as an ion implantation mask; and
selectively removing the buried impurity region to form a channel impurity region, which is connected by a bridge shape with the first and second active regions.

### Claim 3 (depends on 2)

The method of claim 2, wherein the forming of the fin active region comprises:
forming a hard mask layer on the semiconductor substrate; and
forming the fin active region by removing the upper layer to expose the lower layer by using the hard mask layer as an etch mask.

### Claim 4 (depends on 3)

The method of claim 3, wherein the hard mask layer is formed of a silicon nitride layer.

### Claim 5 (depends on 3)

The method of claim 3, further comprising trimming a center portion of the fin active region exposed by the interlayer dielectric layer so that a line width of the fin active region between the first and second active regions is smaller than a line width of the first and second active regions.

### Claim 6 (depends on 3)

The method of claim 3, further comprising removing the hard mask layer.

### Claim 7 (depends on 2)

The method of claim 2, wherein the forming of the interlayer dielectric layer comprises:
forming the interlayer dielectric layer on the semiconductor substrate on which the fin active region was formed; and
selectively removing the interlayer dielectric layer to expose the fin active region on which the gate electrode will be formed.

### Claim 8 (depends on 2)

The method of claim 2, wherein the interlayer dielectric layer is formed of silicon oxide.

### Claim 9 (depends on 8)

The method of claim 8, wherein the silicon oxide layer is formed by a low pressure chemical vapor deposition (LPCVD).

### Claim 10 (depends on 7)

The method of claim 7, further comprising planarizing the interlayer dielectric layer formed on the semiconductor substrate by chemical mechanical polishing (CMP).

### Claim 11 (depends on 2)

The method of claim 2, wherein the impurity is any one of boron, BF2, phosphorus, H, and He.

### Claim 12 (depends on 2)

The method of claim 2, wherein the buried impurity region is formed by an ion implantation at energy of about 30 KeV to about 40 KeV if boron is used as the impurity.

### Claim 13 (depends on 2)

The method of claim 2, wherein the buried impurity region is formed from a predetermined surface depth of the fin active region to a depth the same as or similar to the lower layer of the semiconductor substrate.

### Claim 14 (depends on 2)

The method of claim 2, wherein the buried impurity region is formed by an ion implantation at a density of about 1×1016 atoms/cm2 to about 1×1018 atoms/cm2.

### Claim 15 (depends on 2)

The method of claim 2, wherein the buried impurity region is removed by wet or dry etching.

### Claim 16 (depends on 15)

The method of claim 15, wherein the buried impurity region is removed by using a polysilicon etchant of HF(49%):HNO3(30%):CH3COOH(100%) (Volume 1:3:8) by the wet etching.

### Claim 17 (depends on 15)

The method of claim 15, wherein the buried impurity region is removed by using a reactive gas of CF4:O2 (flow 60:150 sccm) by the dry etching.

### Claim 18 (depends on 1)

The method of claim 1, wherein the gate insulation layer is formed of silicon oxide.

### Claim 19 (depends on 1)

The method of claim 1, wherein the gate insulation layer is formed to a thickness of less than about 130 Å.

### Claim 20 (depends on 1)

The method of claim 1, wherein the gate electrode is formed by a damascene method in which the lower layer of the semiconductor substrate and the interlayer dielectric layer are used as a mold having a predetermined shape.

### Claim 21 (depends on 1)

The method of claim 1, wherein the gate electrode is formed containing any one of a polysilicon layer doped with a non-metallic conductive impurity or tungsten silicide.

### Claim 22 (depends on 1)

The method of claim 1, further comprising forming a source/drain impurity region by ion implanting impurity in the first and second active regions by using the gate electrode as an ion implantation mask.

### Claim 23 (depends on 22)

The method of claim 22, wherein the source/drain impurity region is formed on the first and second active regions that have a depth the same as or similar to the third active region.

### Claim 24

A method of manufacturing a semiconductor device, the method comprising:
forming fin active regions, which are distanced from each other and which are protruded from an upper surface of a lower layer supporting an upper layer of a semiconductor substrate;
forming an interlayer dielectric layer on first and second active regions of both ends of the fin active region to expose a center portion of the fin active region;
ion implanting an impurity to form a buried impurity region with a depth equal to or similar to a height of the fin active region, in the center portion of the fin active region, using the interlayer dielectric layer as an ion implantation mask;
forming a third active region of a bridge shape, which is connected with the first and second active regions and which is distanced vertically from the lower layer, by selectively removing the buried impurity region;
forming a gate insulation layer surrounding the third active region;
forming a gate electrode on the gate insulation layer so that the third active region functions as a channel;
removing the interlayer dielectric layer from the first and second active regions; and
ion implanting a conductive impurity in the first and second active regions to form a source/drain impurity region by using the gate electrode as an ion implantation mask.

### Claim 25

A method of manufacturing an FET, the method comprising:
forming first and second active regions distanced from each other on an insulation layer;
forming a third active region of a bridge shape, which is distanced vertically from an upper surface of the insulation layer and which connects the first and second active regions, the first, second, and third active regions formed from a single-crystal silicon layer;
forming a gate insulation layer to surround the third active region; and
forming a gate electrode on the gate insulation layer so that the third active region functions as a channel.

### Claim 26 (depends on 25)

The method of claim 25, wherein the insulation layer employs a substrate insulation layer of an SOI (Silicon On Insulator) type silicon substrate.

### Claim 27

A method of manufacturing an FET, the method comprising:
forming a fin active region on a substrate insulation layer of an SOI type silicon substrate;
forming an interlayer dielectric layer on first and second active regions of both ends of the fin active region, to expose a center portion of the fin active region;
forming a buried impurity region with a depth equal or similar to a height of the fin active region, in a center portion of the fin active region, by ion implanting an impurity by using the interlayer dielectric layer as an ion implantation mask;
forming a channel impurity region of a bridge shape, which is connected with the first and second active regions and is distanced vertically from the substrate insulation layer, by selectively removing the buried impurity region;
forming a gate insulation layer surrounding the third active region;
forming a gate electrode on the gate insulation layer so that the third active region functions as a channel;
removing the interlayer dielectric layer from the first and second active regions; and
ion implanting a conductive impurity in the first and second active regions to form a source/drain impurity region by using the gate electrode as an ion implantation mask.

### Claim 28 (depends on 1)

The method of claim 1, the third active region distanced vertically from the upper surface of the lower layer such that a lower surface of the third active region is distanced vertically from the upper surface of the lower layer.

### Claim 29 (depends on 25)

The method of claim 25, the third active region distanced vertically from the upper surface of the insulation layer such that a lower surface of the third active region is distanced vertically from the upper surface of the insulation layer.