# US 7,407,837 B2 · Method of manufacturing silicon carbide semiconductor device

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- Number: US 7,407,837 B2
- Document ID: US7407837B2
- Status: Granted
- Kind: B2
- Application number: 11/042,809
- Filed: 2005-01-25
- Published: 2005-08-18
- Granted: 2008-08-05
- Earliest claimed: 2004-01-27
- Assignees: Fuji Electric Holdings Co., Ltd.
- Inventors: Takashi Tsuji
- Web page: https://patentgrep.com/patent/US7407837B2

## CPC

- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 12/031: {of IGBTs}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 30/791: {Arrangements for exerting mechanical stress on the crystal lattice of the channel regions}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/82: Heterojunctions
- H10D 62/8325: {Silicon carbide}
- H10P 30/2042: {into crystalline silicon carbide}
- H10P 30/21: {of electrically active species}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- Y10S 438/931: Silicon carbide semiconductor
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

Stress is exerted to the SiC crystal in the region, in which the carriers of a SiC semiconductor device flow, to change the crystal lattice intervals of the SiC crystal. Since the degeneration of the conduction bands in the bottoms thereof is dissolved, since the inter-band scattering is prevented from causing, and since the effective electron mass is reduced due to the crystal lattice interval change, the carrier mobility in the SiC crystal is improved, the resistance of the SiC crystal is reduced and, therefore, the on-resistance of the SiC semiconductor device is reduced.

## Claims

### Claim 1

A method of manufacturing a SiC semiconductor device, the SiC semiconductor device including a SiC substrate of a first conductivity type; a SiC drift layer of the first conductivity type on the substrate; SiC base regions of a second conductivity type contacting with the drift layer; a SiC source region of the first conductivity type contacting with the base region; a gate electrode covering the portion of the base region that is sandwiched between the drift layer and the source region, with a gate insulator film interposed therebetween; a source electrode contacting commonly with the base region and the source region; and a drain electrode on the back surface of the substrate, the method comprising exerting stress to SiC in the region where carriers flow in order to change the crystal lattice intervals of the SiC by forming a nitride film comprising at least one of AlN and GaN on the sandwiched portion of the base region and forming a SiC layer comprising the region where carriers flow on the nitride film, in order to exert stress on the SiC in the region where carriers flow and thereby change the crystal lattice intervals of the SiC layer comprising the region where carriers flow.

### Claim 2 (depends on 1)

The method according to claim 1, wherein said nitride film is a AlN film.

### Claim 3 (depends on 1)

The method according to claim 1, wherein said nitride film is a GaN film.

### Claim 4 (depends on 1)

The method according to claim 1, wherein said nitride film is a AlGaN film.