# US 7,407,833 B2 · Process for fabricating chip package structure

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- Number: US 7,407,833 B2
- Document ID: US7407833B2
- Status: Granted
- Kind: B2
- Application number: 10/908,075
- Filed: 2005-04-27
- Published: 2005-10-27
- Granted: 2008-08-05
- Earliest claimed: 2004-04-27
- Assignees: Advanced Semiconductor Engineering, Inc.
- Inventors: Jeng-Da Wu
- Web page: https://patentgrep.com/patent/US7407833B2

## CPC

- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 72/01255: {by using masks}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A chip package structure comprising a carrier, a chip and an underfill layer is disclosed. The carrier has a plurality of bumps disposed thereon. The chip has an active surface. The chip is flip-chip bonded and electrically connected to the carrier through the bumps such that the active surface of the chip faces the carrier. The underfill layer is disposed on the carrier between the chip and the carrier such that a gap is maintained between the underfill layer and the chip.

## Claims

### Claim 1

A chip packing process, comprising the steps of:
providing a carrier and a chip, wherein the carrier has a plurality of bumps disposed thereon and the chip has an active surface;
after the step of providing the carrier and the chip, forming an underfill layer on a surface of the carrier having the bumps thereon, wherein the underfill layer is disposed between the bumps but without enclosing the bumps; and
after the step of forming the underfill layer, flip-chip bonding the chip to the carrier so that the chip and the carrier are electrically connected through the bumps.

### Claim 2 (depends on 1)

The chip packaging process of claim 1, wherein the bumps have a height greater than the thickness of the underfill layer.

### Claim 3 (depends on 1)

The chip packaging process of claim 1, wherein the surface of the carrier away from the chip further comprises an array of solder balls attached thereon.

### Claim 4 (depends on 1)

The chip packaging process of claim 1, wherein after flip-chip bonding the chip to the carrier, further comprises forming an array of solder balls on the surface of the carrier away from the chip.

### Claim 5

A chip packaging process, comprising the steps of:
providing a carrier and a chip, wherein the carrier has a plurality of first bumps thereon and the chip has an active surface;
after the step of providing the carrier and the chip, forming an underfill layer on the surface of the carrier, wherein the first bumps are formed on said surface and the underfill layer exposes the first bumps;
after the step of forming the underfill layer, forming a plurality of second bumps over the first bumps such that each of the second bumps is formed on one of the first bumps respectively; and
after the step of forming the second bumps over the first bumps, flip-chip bonding the chip to the carrier so that the chip and the carrier are electrically connected through the first bumps and the second bumps.

### Claim 6 (depends on 5)

The chip packaging process of claim 5, wherein the step of exposing the first bumps in the underfill layer comprises performing a grinding process to remove a portion of the underfill layer till exposing the first bumps.

### Claim 7 (depends on 5)

The chip packaging process of claim 5, wherein the step of forming the second bumps comprises:
forming a photoresist layer over the carrier to cover the underfill layer and the first bumps;
forming a plurality of openings in the photoresist layer to expose the first bumps;
depositing a solder material into the openings;
removing the photoresist layer; and
performing a reflow process to melt and transform the solder material into a plurality of second bumps, wherein each of the second bumps is located on one of the first bumps respectively.

### Claim 8 (depends on 7)

The chip packaging process of claim 7, wherein the photoresist layer comprises a dry film.

### Claim 9 (depends on 7)

The chip packaging process of claim 7, wherein the step of depositing the solder material into the openings comprises a stencil printing process.

### Claim 10 (depends on 5)

The chip packaging process of claim 5, the surface of the carrier away from the chip further comprises an array of solder balls attached thereon.

### Claim 11 (depends on 5)

The chip packaging process of claim 5, wherein after flip-chip bonding the chip to the carrier, further comprises forming an array of solder balls on the surface of the carrier away from the chip.