# US 7,407,829 B2 · Electrically programmable memory element with improved contacts > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,407,829 B2 - Document ID: US7407829B2 - Status: Granted - Kind: B2 - Application number: 10/799,265 - Filed: 2004-03-12 - Published: 2004-12-09 - Granted: 2008-08-05 - Earliest claimed: 1997-10-01 - Assignees: Ovonyx, Inc. - Inventors: Tyler Lowrey; Stanford R. Ovshinsky; Guy C. Wicker; Patrick J. Klersy; Boil Pashmakov; Wolodymyr Czubatyj; Sergey A. Kostylev - Web page: https://patentgrep.com/patent/US7407829B2 ## CPC - G11C 11/5678: {using amorphous/crystalline phase transition storage elements} - G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency - H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors} - H10B 63/82: {the switching components having a common active material layer} - H10N 70/011: {Manufacture or treatment of multistable switching devices} - H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography} - H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect} - H10N 70/821: {Device geometry} - H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices} - H10N 70/8413: {adapted for resistive heating} - H10N 70/8828: {Tellurides, e.g. GeSbTe} - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract A method of making an electrically programmable memory element, comprising: providing a first dielectric layer; forming a conductive material over the first dielectric layer; forming a second dielectric layer over the conductive material; and forming a programmable resistance material in electrical contact with a peripheral surface of the conductive material. ## Claims ### Claim 1 A method of making a plurality of electrically programmable memory elements, comprising: providing a first dielectric layer, said first dielectric layer having an opening, said opening having first and second sidewall surfaces and a bottom surface; forming a conductive layer on said sidewall surfaces and on said bottom surface of said opening; removing at least a portion of said conductive layer from said bottom surface, thereby electrically isolating portions of said conductive layer formed on said first and second sidewalls, one from the other; forming a second dielectric layer contacting said bottom surface or said opening; and forming a programmable resistance material in electrical communication with top portions of said electrically isolated portions of said conductive layer. ### Claim 2 (depends on 1) The method of claim 1, wherein said programmable resistance material is a phase-change material. ### Claim 3 (depends on 1) The method of claim 1, wherein said programmable resistance material includes a chalcogen element. ### Claim 4 (depends on 1) The method of claim 1, wherein said first dielectric layer and said second dielectric layer are formed of the same material. ### Claim 5 (depends on 1) The method of claim 1, wherein said forming a conductive layer comprises conformally depositing said conductive layer. ### Claim 6 (depends on 1) The method of claim 1, wherein said forming a conductive layer comprises anisotropically etching said conductive layer. ### Claim 7 (depends on 1) The method of claim 1, wherein said programmable resistance material is electrically coupled to a top surface of said conductive layer. ### Claim 8 (depends on 1) The method of claim 1, wherein said conductive layer includes a conductive sidewall spacer. ### Claim 9 (depends on 7) The method of claim 7, wherein said top surface of said conductive layer has a lateral dimension less than 1000 Angstroms. ### Claim 10 (depends on 1) The method of claim 1, wherein said conductive layer contacts said bottom surface of said opening. ### Claim 11 (depends on 1) The method of claim 1, wherein said second dielectric layer fills said opening. ### Claim 12 A method of making electrically programmable memory elements, comprising: providing first and second sidewall surfaces and an adjoining bottom surface; forming a conductive layer on said sidewall surfaces and on a portion of said bottom surface, said portion being less than the entire bottom surface and thereby electrically isolating the conductive layer on the first sidewall surface from the conductive layer on the second sidewall surface; forming a dielectric material contacting said bottom surface of said opening; and forming a programmable resistance material in electrical communication with said conductive layer. ### Claim 13 (depends on 12) The method of claim 12, wherein said forming a conductive layer comprises conformally depositing said conductive layer. ### Claim 14 (depends on 12) The method of claim 12, wherein said forming a conductive layer comprises anisotropically etching said conductive layer. ### Claim 15 (depends on 12) The method of claim 12, wherein said programmable resistance material is electrically coupled to a top surface of said conductive layer. ### Claim 16 (depends on 12) The method of claim 12, wherein said dielectric material is formed on said conductive layer before said forming a programmable resistance material. ### Claim 17 (depends on 12) The method of claim 12, wherein said sidewall surface is the sidewall surface of a dielectric layer. ### Claim 18 (depends on 17) The method of claim 17, wherein said dielectric material and said dielectric layer are formed of the same material. ### Claim 19 (depends on 12) The method of claim 12, wherein said portion of the bottom surface is a surface of a substrate. ### Claim 20 (depends on 12) The method of claim 12, wherein said conductive layer has an area of contact with said programmable resistance material, the area of contact having a dimension less than 1000 Angstroms. ### Claim 21 (depends on 12) The method of claim 12, wherein said forming a conductive layer comprises forming a dual-layered conductive sidewall spacer. ### Claim 22 (depends on 21) The method of claim 21, wherein said dual-layered conductive sidewall spacer comprises a first layer having a first resistivity and a second layer having a second resistivity, said first resistivity being less than said second resistivity. ### Claim 23 (depends on 12) The method of claim 12, wherein said conductive layer contacts said bottom surface of said opening. ### Claim 24 (depends on 12) The method of claim 12, wherein said dielectric material fills said opening. ### Claim 25 A method of making an electrical device, comprising: providing first and second sidewall surfaces and an adjoining bottom surface; forming a conductive layer on said sidewall surfaces and on a portion of said bottom surface, said portion being less than the entire bottom surface and thereby electrically isolating the conductive layer on the first sidewall surface from the conductive layer on the second sidewall surface; forming a dielectric material contacting said bottom surface of said opening; and forming a chalcogenide material in electrical communication with said conductive layer. ### Claim 26 (depends on 25) The method of claim 25, wherein said forming a conductive layer comprises conformally depositing said conductive layer. ### Claim 27 (depends on 25) The method of claim 25, wherein said forming a conductive layer comprises anisotropically etching said conductive layer. ### Claim 28 (depends on 25) The method of claim 25, wherein said chalcogenide material is electrically coupled to a top surface of said conductive layer. ### Claim 29 (depends on 25) The method of claim 25, wherein said dielectric material is formed before said forming a chalcogenide material. ### Claim 30 (depends on 25) The method of claim 25, wherein said sidewall surface is the sidewall surface of a dielectric layer. ### Claim 31 (depends on 30) The method of claim 30, wherein said dielectric material and said dielectric layer are formed of the same material. ### Claim 32 (depends on 25) The method of claim 25, wherein said conductive layer includes a conductive sidewall spacer. ### Claim 33 (depends on 25) The method of claim 25, wherein a top surface of said conductive layer is in electrical communication with said chalcogenide material. ### Claim 34 (depends on 33) The method of claim 33, wherein said top surface has an area of contact with said chalcogenide material, the area of contact having a dimension less than 1000 Angstroms. ### Claim 35 (depends on 25) The method of claim 25, wherein said portion of the bottom surface is a surface of a substrate. ### Claim 36 (depends on 32) The method of claim 32, wherein said conductive sidewall spacer is a dual-layered conductive sidewall spacer. ### Claim 37 (depends on 36) The method of claim 36, wherein said dual-layered conductive sidewall spacer comprises a first layer having a first resistivity and a second layer having a second resistivity, said first resistivity being less than said second resistivity. ### Claim 38 (depends on 25) The method of claim 25, wherein said conductive layer contacts said bottom surface of said opening. ### Claim 39 (depends on 25) The method of claim 25, wherein said dielectric material fills said opening. ### Claim 40 A method of making an electrical device, comprising: forming electrical contacts by a method comprising: providing first and second sidewall surfaces and an adjoining bottom surface; forming a conductive layer on said sidewall surfaces and on a portion of said bottom surface, said portion being less than the entire bottom surface and thereby electrically isolating the conductive layer on the first sidewall surface from the conductive layer on the second sidewall surface; forming a dielectric material contacting said bottom surface of said opening; and forming a chalcogenide material in electrical communication with said electrical contact. ### Claim 41 (depends on 40) The method of claim 40, wherein said forming a conductive layer comprises conformally depositing said conductive layer. ### Claim 42 (depends on 40) The method of claim 40, wherein said forming a conductive layer comprises anisotropically etching said conductive layer. ### Claim 43 (depends on 40) The method of claim 40, wherein said chalcogenide material is formed after forming said electrical contact. ### Claim 44 (depends on 40) The method of claim 40, wherein said electrical contact is a conductive sidewall spacer. ### Claim 45 (depends on 40) The method of claim 40, wherein said sidewall surface is the sidewall surface of a dielectric layer. ### Claim 46 (depends on 40) The method of claim 40, wherein said portion of the bottom surface is a surface of a substrate. ### Claim 47 (depends on 40) The method of claim 40, wherein said conductive layer has an area of contact with said chalcogenide material, the area of contact having a dimension less than 1000 Angstroms. ### Claim 48 (depends on 40) The method of claim 40, wherein said forming a conductive layer comprises forming a dual-layered conductive sidewall spacer. ### Claim 49 (depends on 48) The method of claim 48, wherein said dual-layered conductive sidewall spacer comprises a first layer having a first resistivity and a second layer having a second resistivity, said first resistivity being less than said second resistivity. ### Claim 50 (depends on 40) The method of claim 40, wherein said conductive layer contacts said bottom surface of said opening. ### Claim 51 (depends on 40) The method of claim 40, wherein said dielectric material fills said opening. ### Claim 52 A method of making an electrical device, comprising: forming electrical contacts by a method comprising: providing first and second sidewall surfaces and an adjoining bottom surface; forming a conductive layer on said sidewall surfaces and on a portion of said bottom surface, said portion being less than the entire bottom surface and thereby electrically isolating the conductive layer on the first sidewall surface from the conductive layer on the second sidewall surface; forming a dielectric material contacting said bottom surface of said opening; and forming a phase-change material in electrical communication with said electrical contact. ### Claim 53 (depends on 52) The method of claim 52, wherein said forming a conductive layer comprises conformally depositing said conductive layer. ### Claim 54 (depends on 52) The method of claim 52, wherein said forming a conductive layer comprises anisotropically etching said conductive layer. ### Claim 55 (depends on 52) The method of claim 52, wherein said phase-change material is formed after forming said electrical contact. ### Claim 56 (depends on 52) The method of claim 52, wherein said electrical contact is a conductive sidewall spacer. ### Claim 57 (depends on 52) The method of claim 52, wherein said sidewall surface is the sidewall surface of a dielectric layer. ### Claim 58 (depends on 52) The method of claim 52, wherein said phase-change material comprises at least one chalcogen element. ### Claim 59 (depends on 52) The method of claim 52, wherein said conductive layer has an area of contact with said phase-change material, the area of contact having a dimension less than 1000 Angstroms. ### Claim 60 (depends on 52) The method of claim 52, wherein said portion of the bottom surface is a surface of a substrate. ### Claim 61 (depends on 52) The method of claim 52, wherein said forming a conductive layer comprises forming a dual-layered conductive sidewall spacer. ### Claim 62 (depends on 61) The method of claim 61, wherein said dual-layered conductive sidewall spacer comprises a first layer having a first resistivity and a second layer having a second resistivity, said first resistivity being less than said second resistivity. ### Claim 63 (depends on 52) The method of claim 52, wherein said conductive layer contacts said bottom surface of said opening. ### Claim 64 (depends on 52) The method of claim 52, wherein said dielectric material fills said opening.