# US 7,407,828 B2 · CMOS image sensor and manufacturing method thereof

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- Number: US 7,407,828 B2
- Document ID: US7407828B2
- Status: Granted
- Kind: B2
- Application number: 11/293,082
- Filed: 2005-12-05
- Published: 2006-06-15
- Granted: 2008-08-05
- Earliest claimed: 2004-12-15
- Assignees: Dongbu Electronics Co., Ltd.
- Inventors: Sang-Gi Lee
- Web page: https://patentgrep.com/patent/US7407828B2

## CPC

- H10F 39/014: {of CMOS image sensors}
- H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
- H10F 39/807: {Pixel isolation structures}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

A gate insulation layer with a high dielectric constant for a CMOS image sensor formed by a damascene process. A silicide layer on a gate electrode layer is formed in both a pixel region and a peripheral circuit region, and a silicide layer on a source/drain region is formed only in a peripheral circuit.

## Claims

### Claim 1

A method for manufacturing a CMOS image sensor, comprising:
forming a dummy gate stack with a gate insulation layer and a dummy gate electrode layer on a semiconductor substrate;
forming a gate spacer layer on at least a sidewall of the dummy gate stack;
forming a source/drain region on the semiconductor substrate by an ion implantation process using the dummy gate stack and the gate spacer layer as an implantation mask;
diffusing the implanted impurity ions by using a rapid thermal process;
removing the dummy gate stack to expose a partial surface of the semiconductor substrate;
forming an insulation layer with a high dielectric constant on the exposed surface of the semiconductor substrate;
forming a gate electrode layer on the insulation layer with a high dielectric constant;
sequentially forming a liner layer and a dummy pre-metal dielectric layer on the entire surface of the semiconductor substrate having the gate electrode layer thereon;
partially removing the dummy pre-metal dielectric layer and the liner layer to expose a surface of the gate electrode by a planarization process;
sequentially removing the dummy pre-metal dielectric layer and the liner layer in a peripheral circuit region by using a mask layer pattern to cover a pixel region;
forming a suicide layer on the gate electrode layer in the pixel region and on the gate electrode layer and the source/drain region in the peripheral circuit region by a silicidation process; and
removing the dummy pre-metal dielectric layer and the liner layer remaining in the pixel region.

### Claim 2 (depends on 1)

The method of claim 1, further comprising, after forming the dummy gate stack, implanting impurity ions for forming an extended source/drain region of an LDD structure by using the gate stack.

### Claim 3 (depends on 1)

The method of claim 1, wherein the forming of the insulation layer with a high dielectric constant is performed at a temperature under 600° C.

### Claim 4 (depends on 1)

The method of claim 1, wherein the liner layer is formed as a nitride layer.