# US 7,407,247 B2 · Controller which generates data suitable for inkjet printhead

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- Number: US 7,407,247 B2
- Document ID: US7407247B2
- Status: Granted
- Kind: B2
- Application number: 11/521,388
- Filed: 2006-09-15
- Published: 2007-01-11
- Granted: 2008-08-05
- Earliest claimed: 2004-09-27
- Assignees: Silverbrook Research Pty Ltd
- Inventors: Simon Robert Walmsley
- Web page: https://patentgrep.com/patent/US7407247B2

## CPC

- H04N 1/502: {Reproducing the colour component signals dot-sequentially or simultaneously in a single or in adjacent picture-element positions}
- B41J 2/17546: {electronically}
- B41J 29/393: Devices for controlling or analysing the entire machine {; Controlling or analysing mechanical parameters involving printing of test patterns}
- G06K 15/02: using printers
- G06K 15/102: {using ink jet print heads}
- G06K 15/1852: {involving combining data of different types}
- H04N 1/387: Composing, repositioning or otherwise {geometrically} modifying originals
- H04N 1/603: {controlled by characteristics of the picture signal generator or the picture reproducer}
- G06K 2215/0082: Architecture adapted for a particular function
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- B41J: TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- G06K: GRAPHICAL DATA READING (image or video recognition or understanding G06V); PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS

## Abstract

A print controller for an inkjet printhead is provided. The print controller has contone decompression circuitry for decompressing a contone layer of compressed page data, bi-level decompression circuitry for decompressing a bi-level layer of the compressed page data, halftoner and compositor circuitry for halftoning the decompressed contone planes to associated bi-level versions and compositing the decompressed bi-level layer over the halftoned contone layers, and printhead interface circuitry for receiving the halftoned and composited data so as to generate print data suitable for printing by the printhead.

## Claims

### Claim 1

A print controller for an inkjet printhead, the print controller comprising:
contone decompression circuitry for decompressing a contone layer of compressed page data;
bi-level decompression circuitry for decompressing a bi-level layer of the compressed page data;
halftoner and compositor circuitry for halftoning the decompressed contone planes to associated bi-level versions and compositing the decompressed bi-level layer over the halftoned contone layers; and
printhead interface circuitry for receiving the halftoned and composited data so as to generate print data suitable for printing by the printhead.

### Claim 2 (depends on 1)

A print controller as claimed in claim 1, further comprising tag encoder circuitry for establishing infrared tag data on infrared tags according to protocols associated with the compressed page data.

### Claim 3 (depends on 2)

A print controller as claimed in claim 2, wherein the halftoner and compositor circuitry composites the infrared tags with the halftoned and composited data.

### Claim 4 (depends on 1)

A print controller as claimed in claim 1, in which the contone decompression circuitry is in the form of JPEG decoder circuitry.

### Claim 5 (depends on 1)

A print controller as claimed in claim 1, in which the bi-level decompression circuitry is in the form of G4 fax decoder circuitry.

### Claim 6 (depends on 1)

A print controller as claimed in claim 1, further comprising buffer circuitry for buffering the transfer of data to the halftoner and compositor circuitry.

### Claim 7 (depends on 1)

A print controller as claimed in claim 1, further comprising line loader and formatter circuitry for receiving dot data from the halftoner and compositor circuitry so as to store the dot data for lines to be printed in memory circuitry of the controller and format said lines into an order required by the printhead interface circuitry.

### Claim 8 (depends on 7)

A print controller as claimed in claim 7, in which the memory circuitry is in the form of DRAM.