Method and apparatus for enforcing independence of processors on a single IC
AssigneeMotorola, Inc.
InventorsKenneth C. Fuchs, Brian W. Pruss, Timothy M. Langham
Life of this patent
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Abstract
A single-chip integrated circuit comprising a first processor for executing a plurality of applications, a second processor for executing a plurality of applications, at least one of a) at least one embedded peripheral and b) at least one memory, and a bus monitor for allowing access to the at least one of a) the at least one embedded peripheral and b) the at least one memory, if the access is allowed, wherein the bus monitor comprises a mapping of access rights to the at least one of a) the at least one embedded peripheral and b) the at least one memory for the first processor and the second processor is disclosed.
Claims20
A single-chip integrated circuit, comprising:
- a first processor for executing a plurality of applications;
- a second processor for executing a plurality of applications;
- at least one of a) at least one embedded peripheral and b) at least one memory;
- and
- a bus monitor for monitoring a system bus for access requests for the first and second processors comprising the single-chip integrated circuit and sharing the system bus, wherein each access request comprises an address, the bus monitor further for examining permissions associated with the address when the address falls within an address range for the corresponding access request, and allowing access to the at least one of a) the at least one embedded peripheral and b) the at least one memory if permissions allow access,
- wherein the bus monitor comprises a mapping of access rights to the at least one of a) the at least one embedded peripheral and b) the at least one memory for the first processor and the second processor.
A method for enforcing independence of processors in a single-chip integrated circuit, comprising the steps of:
- monitoring by a bus monitor a system bus for an access request, wherein the access request comprises an address and wherein the access request is sent by a processor on the single-chip integrated circuit;
- determining whether the address is within an address range for the access request by comparing the address with the address range, wherein the bus monitor comprises at least one address range;
- examining permissions associated with the address, if the address falls within the address range;
- and
- allowing access to the address, if the permissions allow access,
- wherein the single-chip integrated circuit comprises at least two processors sharing access to a single system bus.
A single-chip integrated circuit, comprising:
- a bus monitor for allowing access to a at least one of a) a at least one embedded peripheral and b) a at least one memory, if the access is allowed for a processor,
- wherein the bus monitor comprises a mapping of access rights to the at least one of a) the at least one embedded peripheral and b) the at least one memory for the processor and
- wherein the bus monitor comprises:
- i) means for monitoring a system bus for an access request from the processor, wherein the access request comprises an address associated with the access request, and wherein the system bus connects the processor to the at least one of a) one embedded peripheral and b) the at least one memory;
- ii) means for determining whether the address is within an address range for the access request by comparing the address with the address range;
- iii) means for examining permissions associated with the address, if the address falls within the address range;
- and
- iv) means for allowing access to the address, if the permissions allow access.
Dependencies are inferred from the claim text.