Method and apparatus for constructing and optimizing a skew of a clock tree
AssigneeFujitsu Limited
InventorDaisuke Fukuda
Life of this patent
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Abstract
An apparatus for supporting a design of a circuit including a plurality of elements, comprising: an acquiring unit that acquires a clock tree of the circuit; a constructing unit that constructs, based on the clock tree, a plurality of groups each of which includes a part of elements of same skew; an analyzing unit that performs an analysis of a timing of an inter-group path between two of the groups; and an output unit that outputs a result of the analysis.
Claims9
An apparatus for supporting a design of a circuit, comprising:
- an acquiring unit that acquires a clock tree of the circuit;
- a constructing unit that constructs, based on the clock tree, a plurality of groups of elements in the circuit each of which includes a plurality of elements having same clock skew;
- an analyzing unit that performs an analysis of a timing of an inter-group path between a first group and a second group among the groups;
- and
- an output unit that outputs a result of the analysis, wherein:
- the constructing unit further constructs, when the inter-group path is a critical path, a third group including at least one element connected with the inter-group path and excluded from the first group, and
- the analyzing unit performs an analysis of the timing of inter-group path between the third group and one of the other groups.
A method for supporting a design of a circuit, comprising:
- acquiring a clock tree of the circuit;
- constructing, based on the clock tree, a plurality of groups of elements in the circuit, each of which includes a plurality of elements having a common clock skew;
- performing an analysis of timing of an inter-group path between a first group and a second group among the groups;
- outputting a result of the analysis;
- constructing, when the inter-group path is a critical path, a third group including at least one element connected with the inter-group path and excluded from a a first group;
- and
- performing an analysis of the timing of inter-group path(s) between the third group and one of the other groups.
A computer-readable recording medium for supporting a design of a circuit, wherein the computer program causes the computer to execute:
- acquiring a clock tree of the circuit;
- constructing, based on the clock tree, a plurality of groups of elements in the circuit, each of which includes a plurality of elements having a common clock skew;
- performing an analysis of timing of an inter-group path between a first group and a second group among the groups;
- outputting a result of the analysis;
- constructing, when the inter-group path is a critical path, a third group including at least one element connected with the inter-group path and excluded from the first group;
- and
- performing an analysis of the timing of an inter-group path between the third group and one of the other groups.
Dependencies are inferred from the claim text.