Timing constraints methodology for enabling clock reconvergence pessimism removal in extracted timing models
AssigneeLSI Corporation
InventorPeter F. Lindberg
Life of this patent
Estimating the term…
Abstract
A method of enabling CRPR in an ETM. In an exemplary embodiment, the method includes locating a plurality of clocks defined within a core. The method may also include determining if one of the plurality of clocks are clocking data both within the core and outside of the core. A CRPR clock for an output pin of a last cell in a clock path common to an internal register clock pin and one of the plurality of clocks clocking data clocking data both within the core and outside of the core may be defined. A static timing analysis tool may be employed to calculate the CRPR from the CRPR clock.
Claims13
A method for enabling clock reconvergence pessimism removal (CRPR) in an extracted timing model (ETM), the method comprising:
- locating a plurality of clocks defined within a core;
- determining if one of the plurality of clocks are clocking data both within the core and outside of the core, said determining if one of the plurality of clocks are clocking data both within the core and outside of the core comprising:
- connecting input pins with input ports and output pins with output ports;
- defining standard time constraints and chip level constraints;
- applying global timing derating;
- activating a CRPR algorithm;
- and
- generating a timing report on each of the output ports;
- generating a CRPR clock for an output pin of a last cell in a clock path common to an internal register clock pin and one of the plurality of clocks clocking data both within the core and outside of the core;
- and
- utilizing a static timing analysis tool to calculate the CRPR from the CRPR clock.
A computer-readable medium having computer-executable instructions for performing a method for enabling clock reconvergence pessimism removal (CRPR) in an extracted timing model (ETM), the method comprising:
- locating a plurality of clocks defined within a core;
- determining if one of the plurality of clocks are clocking data both within the core and outside of the core, said determining if one of the plurality of clocks are clocking data both within the core and outside of the core comprising:
- connecting input pins with input ports and output pins with output ports;
- defining standard time constraints and chip level constraints;
- applying global timing derating;
- activating a CRPR algorithm;
- and
- generating a timing report on each of the output ports;
- generating a CRPR clock for an output pin of a last cell in a clock path common to an internal register clock pin and one of the plurality of clocks clocking data both within the core and outside of the core;
- and
- utilizing a static timing analysis tool to calculate the CRPR from the clock delay information.
Dependencies are inferred from the claim text.