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US 7,406,647 B2Granted
Systems and methods for forward error correction in a wireless communication network
AssigneePulse-LINK, Inc.
InventorIsmail Lakkis
Life of this patent
Estimating the term…
Abstract
A forward error correction encoder encodes input data words into code words that comprise a parity matrix. In one aspect, the encoder is optimized based on the properties of the parity matrix in order to reduce routing overhead size.
Claims19
An FEC encoder, comprising:
- a plurality of block cyclic shift registers;
- a plurality of fixed connections between each of the plurality of block cyclic shift registers;
- and
- a plurality of XOR gates coupled to the plurality of fixed connections, the fixed connections fixed such that the first fixed connection between each of the plurality of block cyclic shift registers is coupled to the first of the plurality of XOR gates, the second fixed connection between each of the plurality of block cyclic shift registers is connected to the second of the plurality of XOR gates, and so on until the last of the fixed connections between each of the block cyclic shift registers is coupled to the last of the plurality of XOR gates.
1 more element
A wireless transmitter, comprising:
- a processor configured to generate data to be transmitted by the transmitter, and
- an FEC encoder configured to generate a code word based on the data, the FEC encoder comprising:
- a plurality of block cyclic shift registers configured to receive the data and shift it through the plurality of block cyclic shift registers;
- a plurality of fixed connections between each of the plurality of block cyclic shift registers configured to allow the data to be shifted through the plurality of block cyclic shift registers;
- and
- a plurality of XOR gates coupled to the plurality of fixed connections, the fixed connections fixed such that the first fixed connection between each of the plurality of block cyclic shift registers is coupled to the first of the plurality of XOR gates, the second fixed connection between each of the plurality of block cyclic shift registers is connected to the second of the plurality of XOR gates, and so on until the last of the fixed connections between each of the block cyclic shift registers is coupled to the last of the plurality of XOR gates.
3 more elements
Dependencies are inferred from the claim text.