Test pattern generating apparatus, method for automatically generating test patterns and computer program product for executing an application for a test pattern generating apparatus

A method for automatically generating test patterns comprising:

• extracting a plurality of layout parameters of a circuit under test based on gate net information and layout information of the circuit, and linking the layout parameters with corresponding fault models respectively;
• calculating a weight for each fault model linked with the layout parameters for both a plurality of undetected faults of the fault model and a plurality of faults detected by a plurality of test patterns, based on process failure information and layout parameter information;
• generating the test patterns in accordance with the weight of each fault model linked with the layout parameters;
• selecting a plurality of effective test patterns from the generated test patterns, based on the calculated weight;
• and
• determining whether a fault coverage of the selected test patterns satisfies a required fault coverage set to the layout parameter information;
• wherein
• the layout parameters include at least one of a metal wire, a pair of adjacent wires, a via, or a primitive cell,
• the layout parameter information includes at least one of a length of the metal wire, a length of adjacent part of wires, a quantity of vias, a quantity of vias in a critical path or a length of the metal wire on a critical path, or an area of the primitive cell;
• and
• the plurality of faults detected by the plurality of test patterns include information on frequencies of short, open, restive short, or resistive open failure occurrences.

A computer program product for executing an application for a test pattern generating apparatus comprising:

• instructions configured to extract a plurality of layout parameters of a circuit under test based on gate net information and layout information of the circuit, and to link the layout parameters with corresponding fault models respectively;
• instructions configured to calculate a weight for each fault model linked with the layout parameters for both a plurality of undetected faults of the fault model and a plurality of faults detected by a plurality of test patterns, based on process failure information and layout parameter information;
• instructions configured to generate the test patterns in accordance with the weight of each fault model linked with the layout parameters;
• instructions configured to select a plurality of effective test patterns from the generated test patterns, based on the calculated weight;
• and instructions configured to judge whether a fault coverage of the selected test patterns satisfies a required fault coverage set to the layout parameter information;
• wherein
• the layout parameters include at least one of a metal wire, a pair of adjacent wires, a via, or a primitive cell,
• the layout parameter information includes at least one of a length of the metal wire, a length of adjacent part of wires, a quantity of vias, a quantity of vias in a critical path or a length of the metal wire on a critical path, or an area of the primitive cell;
• and
• the plurality of faults detected by the plurality of test patterns include information on frequencies of short, open, restive short, or resistive open failure occurrences.