Techniques for capturing signals at output pins in a programmable logic integrated circuit

A method for capturing a board level interconnect test signal, the method comprising:

• configuring a pin in a programmable logic integrated circuit (IC) to function only as an output pin during a user mode of the programmable logic integrated circuit;
• scanning a test instruction into the programmable logic IC during a boundary scan test, wherein the programmable logic IC is coupled to a second IC through board level interconnects;
• enabling a first input buffer using a first logic gate in the programmable logic IC during the boundary scan test in response to the test instruction, wherein the first logic gate receives the test instruction and a first configuration data signal;
• disabling an output buffer using a second logic gate in the programmable logic IC during the boundary scan test in response to the test instruction to prevent contention with the board level interconnect test signal at the pin, the first input buffer and the output buffer being coupled to the pin, wherein the second logic gate receives the test instruction and an output enable signal;
• capturing the board level interconnect test signal from one of the board level interconnects at the pin using the first input buffer during the boundary scan test;
• disabling the first input buffer using the first logic gate after the boundary scan test during the user mode in response to the test instruction and the first configuration data signal;
• and
• enabling the output buffer using the second logic gate in response to the test instruction and the output enable signal.

A programmable logic integrated circuit comprising:

• a pin configured to operate only as an output pin during a user mode of the programmable logic integrated circuit;
• an output buffer coupled to the pin;
• a first input buffer coupled to the pin;
• a first logic gate that receives a test instruction and an output enable signal, wherein the first logic gate disables the output buffer in response to the test instruction during a boundary scan test, wherein the first logic gate enables the output buffer in response to the output enable signal and the test instruction;
• and
• a second logic gate that receives the test instruction and a first configuration data signal, wherein the second logic gate enables the first input buffer in response to the test instruction during the boundary scan test to capture an external board level interconnect test signal applied to the pin, wherein the second logic gate disables the first input buffer in response to the first configuration data signal and the test instruction during the user mode, the first input buffer is enabled only during the boundary scan test, and the programmable logic integrated circuit is part of a scan chain during the boundary scan test.