System and method for optimized test and configuration throughput of electronic circuits

A method for testing or programmably configuring a plurality of electronic circuits, comprising the steps of:

• Providing at least one first sub-system including
• a first test bus, and
• a plurality of first addressable test controllers coupled to the first test bus and coupleable to a plurality of first electronic circuits, the first electronic circuits being communicably coupleable to the first test bus via the first addressable test controllers, respectively;
• providing at least one second sub-system including
• a second test bus, and
• a plurality of second addressable test controllers coupled to the second test bus and coupleable to a plurality of second electronic circuits, the second electronic circuits being communicably coupleable to the second test bus via the second addressable test controllers, respectively;
• unloading the plurality of electronic circuits from a selected one of first and second pluralities of test fixtures corresponding to the first and second sub-systems, respectively, and loading the plurality of electronic circuits into the selected one of first and second pluralities of test fixtures by electronic circuit handling equipment;
• in an applying step, applying, substantially in parallel, input data to a selected one of the plurality of first electronic circuits and the plurality of second electronic circuits by the plurality of the first addressable test controllers and the plurality of the second addressable test controllers, respectively;
• and
• in a receiving step, optionally receiving, substantially in parallel, output data from the selected one of the plurality of first circuits and the plurality of second circuits by the plurality of the first addressable test controllers and the plurality of the second addressable test controllers, respectively,
• wherein the applying and receiving steps are performed by the plurality of the first addressable test controllers and the plurality of the second addressable test controllers for testing or configuring the first and second electronic circuits, respectively, in an alternating fashion,
• wherein at least one of the steps of unloading and loading the electronic circuits corresponding to one of the first and second sub-systems is performed by the handling equipment while the electronic circuits corresponding to the other one of the first and
• second sub-systems are being tested or configured, and Conclusion
• wherein the time required for testing or configuring the electronic circuits is substantially equal to the time required for unloading and loading the electronic circuits.

A method of testing or programmably configuring a plurality of electronic circuits, for use in conjunction with a test system configured to test multiple partitions of circuits in a concurrent fashion, the method comprising the steps of:

• partitioning the plurality of electronic circuits into multiple partitions of circuits, each of the respective partitions including N circuits, N being a positive integer;
• for each partition of N circuits:
• in a loading step, loading the partition of N circuits into the teat system, a first amount of time L being required to load each circuit included in the partition of N circuits;
• in a testing or programmably configuring step, testing or programmably configuring the partition of N circuits using the test system, a second amount of time TC being required to test or programmably configure the N circuits included in the partition of N circuits;
• and
• in an unloading step, unloading the partition of N circuits from the test system, a third amount of time U being required to unload each circuit included in the partition of N circuits,
• wherein the loading, the testing or programmably configuring, and the unloading steps for each partition of N circuits are performed sequentially and at least partially concurrently with the loading, the testing or programmably configuring, and the unloading steps for at least one other partition of N circuits, and
• wherein N is equal to ceiling[TC/[U+L]], N corresponding to the number of circuits included in at least two respective partitions of circuits being tested or programmably configured in a concurrent fashion by the test system.