Method and apparatus for utilizing an exception handler to avoid hanging up a CPU when a peripheral device does not respond
AssigneeCisco Technology, Inc.
InventorSampath Kumar
Life of this patent
Estimating the term…
Abstract
A method and apparatus utilizes an exception handler to implement LOAD and STORE instructions for moving data between a peripheral device and CPU registers. TLB entries for peripheral devices are flagged invalid during initialization and an exception handler occurs when LOAD or STORE instructions are executed by the CPU. The exception handler programs a data mover to perform the LOAD or STORE instruction so that the CPU will not hang up in the event that the peripheral device does not respond thereby avoiding reset of the SOC by the watchdog timer. If the peripheral device does not respond before an exception handler timer expires an error is indicated by the exception handler.
Claims18
A method for accessing a first peripheral device coupled via a bus to a system-on-a-chip (SOC) including a CPU, having a Memory Management Unit (MMU) for performing address translation, where the MMU includes a Translation Look-aside Buffer (TLB) having a first TLB entry for the first peripheral device, with the SOC further including a data mover for transferring data between the first peripheral device and memory independent of the CPU, and a watchdog timer that resets the SOC after a watchdog time-out period expires, said method comprising:
- flagging the first TLB entry as invalid;
- executing a LOAD or STORE instruction at the CPU for accessing the first peripheral device to transfer data between the first peripheral device and a register on the CPU, where an exception handler occurs when the first TLB entry is accessed during address translation;
- with the exception handler:
- programming the data mover to move data between the first peripheral device and memory and to transfer data between memory and a CPU register so that the CPU does not execute LOAD or STORE instructions with the first peripheral device as a source or destination to avoid hanging up the CPU and preventing the watchdog timer from being reset before the watch dog timer period expires.
A system for accessing a first peripheral device coupled via a bus to a system-on-a-chip (SOC) including a CPU, having a Memory Management Unit (MMU) for performing address translation, where the MMU includes a Translation Look-aside Buffer (TLB)having a first TLB entry for the first peripheral device, with the SOC further including a data mover for transferring data between the first peripheral device and memory independent of the CPU, and a watchdog timer that resets the SOC after a watchdog time-out period expires, said system comprising:
- means for flagging the first TLB entry as invalid;
- means for executing a LOAD or STORE instruction at the CPU for accessing the first peripheral device to transfer data between the first peripheral device and a register on the CPU, where an exception handler occurs when the first TLB entry is accessed during address translation;
- means for programming the data mover to move data between the first peripheral device and memory and to transfer data between memory and a CPU register so that the CPU does not execute LOAD or STORE instructions with the first peripheral device as a source or destination to avoid hanging up the CPU and preventing the watchdog timer from being reset before the watch dog timer period expires.
One or more computer readable storage media encoded with software comprising computer executable instructions and when the software is executed operable to:
- access a first peripheral device coupled via a bus to a system-on-a-chip (SOC) including a CPU, having a Memory Management Unit (MMU) for performing address translation, where the MMU includes a Translation Look-aside Buffer (TLB) having a first TLB entry for the first peripheral device, with the SOC further including a data mover for transferring data between the first peripheral device and memory independent of the CPU, and a watchdog timer that resets the SOC after a watchdog time-out period expires;
- flag the first TLB entry as invalid;
- execute a LOAD or STORE instruction at the CPU for accessing the first peripheral device to transfer data between the first peripheral device and a register on the CPU, where an exception handler occurs when the first TLB entry is accessed during address translation;
- program the data mover to move data between the first peripheral device and memory and to transfer data between memory and a CPU register so that the CPU does not execute LOAD or STORE instructions with the first peripheral device as a source or destination to avoid hanging up the CPU and preventing the watchdog timer from being reset before the watchdog time-out period expires.
A method for accessing a first peripheral device coupled via a bus to a system including a CPU, having a Memory Management Unit (MMU) for performing address translation, where the MMU includes a Translation Look-aside Buffer (TLB) having a first TLB entry for the first peripheral device, with the system further including a data mover for transferring data between the first peripheral device and memory independent of the CPU, and a watchdog timer that resets the system after a watchdog time-out period expires, said method comprising:
- flagging the first TLB entry as invalid;
- executing a LOAD or STORE instruction at the CPU for accessing the first peripheral device to transfer data between the first peripheral device and a register on the CPU, where an exception handler occurs when the first TLB entry is accessed during address translation;
- with the exception handler:
- programming the data mover to move data between the first peripheral device and memory and to transfer data between memory and a CPU register so that the CPU does not execute LOAD or STORE instructions with the first peripheral device as a source or destination to avoid hanging up the CPU and preventing the watchdog timer from being reset before the watchdog time-out period expires.
A system for accessing a first peripheral device coupled via a bus to a system including a CPU, having a Memory Management Unit (MMU) for performing address translation, where the MMU includes a Translation Look-aside Buffer (TLB) having a first TLB entry for the first peripheral device, with the system further including a data mover for transferring data between the first peripheral device and memory independent of the CPU, and a watchdog timer that resets the system after a watchdog time-out period expires, said system comprising:
- means for flagging the first TLB entry as invalid;
- means for executing a LOAD or STORE instruction at the CPU for accessing the first peripheral device to transfer data between the first peripheral device and a register on the CPU, where an exception handler occurs when the first TLB entry is accessed during address translation;
- means for programming the data mover to move data between the first peripheral device and memory and to transfer data between memory and a CPU register so that the CPU does not execute LOAD or STORE instructions with the first peripheral device as a source or destination to avoid hanging up the CPU and preventing the watchdog timer from being reset before the watchdog time-out period expires.
One or more computer readable storage media encoded with software comprising computer executable instructions and when the software is executed operable to:
- access a first peripheral device coupled via a bus to a system including a CPU, having a Memory Management Unit (MMU) for performing address translation, where the MMU includes a Translation Look-aside Buffer (TLB) having a first TLB entry for the first peripheral device, with the system further including a data mover for transferring data between the first peripheral device and memory independent of the CPU, and a watchdog timer that resets the system after a watchdog time-out period expire;
- flag the first TLB entry as invalid;
- execute a LOAD or STORE instruction at the CPU for accessing the first peripheral device to transfer data between the first peripheral device and a register on the CPU, where an exception handler occurs when the first TLB entry is accessed during address translation;
- program the data mover to move data between the first peripheral device and memory and to transfer data between memory and a CPU register so that the CPU does not execute LOAD or STORE instructions with the first peripheral device as a source or destination to avoid hanging up the CPU and preventing the watchdog timer from being reset before the watch dog timer period expires.
Dependencies are inferred from the claim text.