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US 7,406,628 B2Granted
Simulated error injection system in target device for testing host system
AssigneeSeagate Technology LLC
InventorsBrian T. Edgar, Feng Li, Mark A. Schmidt
Life of this patent
Estimating the term…
Abstract
A method and device are provided that use a sequencer in the device to control interactions on an interface bus. The sequencer is programmed to interrupt a co-processor before execution of a command. Based on the interrupt signal and a stored error mode page, a false error condition is initiated by further programming the sequencer to operate abnormally. After recovery from the error condition, the sequencer is reprogrammed to operate normally.
Claims20
A method comprising the steps of:
- receiving a command at a device through a sequencer that controls interactions on a small computer system interface bus;
- programming the sequencer to interrupt a co-processor before executing the command;
- and
- executing a set of instructions on the co-processor based on a stored error mode page so that a false error condition is generated, wherein executing a set of instructions comprises reprogramming the sequencer so that it is prevented from entering a reselection phase to re-establish a connection across the small computer system interface bus.
1 more element
A device comprising:
- a sequencer adapted to be connected to a small computer system parallel interface bus;
- a co-processor, coupled to the sequencer and capable of being interrupted by the sequencer and of providing instructions to the sequencer;
- and
- an instruction storage component, communicatively connected to the co-processor and containing processor-executable instructions that are designed to initiate an error condition after the sequencer sends an interrupt to the co-processor, wherein the processor-executable instructions comprise instructions for preventing the sequencer from entering a reselection phase for a period of time so that the sequencer does not establish a connection across the small computer system parallel interface bus.
1 more element
A method comprising:
- receiving a command at a device through a sequencer to generate a false data miscompare error;
- programming the sequencer to interrupt a co-processor before executing the command;
- and
- executing a set of instructions comprising reprogramming the sequencer so that it is prevented from entering a reselection phase to re-establish a connection across a small computer system interface bus;
- reading data from a storage medium into a memory;
- changing at least some of the data in the memory to form corrupted data;
- and passing the corrupted data as the data read from the storage medium.
4 more elements
A method comprising:
- receiving a command at a device through a sequencer indicating that a false timeout error should be generated;
- programming the sequencer to interrupt a co-processor before executing the command;
- and
- executing a set of instructions comprising reprogramming the sequencer so that it is prevented from entering a reselection phase to re-establish a connection across a small computer system interface bus;
- processing a portion of the command;
- and stopping the processing of the command before completing the command without indicating that processing of the command has stopped.
3 more elements
A method comprising:
- receiving a command at a storage device through a sequencer to generate a false error, the command comprising at least one sense parameter;
- programming the sequencer to interrupt a co-processor before executing the command;
- and
- executing a set of instructions comprising reprogramming the sequencer so that it is prevented from entering a reselection phase to re-establish a connection across a small computer system interface bus;
- and
- generating a false error message from the storage device that indicates that an error has occurred when it has not occurred, the false error message describing the error in part by including the at least one sense parameter.
3 more elements
Dependencies are inferred from the claim text.