Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions

A method of reducing power consumption in a processor, the method comprising:

• detecting during execution of the processor that a target address of a branch instruction is located in a memory page includes a branch instruction address of the branch instruction, wherein the detecting is carried out by a pre-decoder;
• storing an indicator that is associated with the detecting;
• suppressing, in response to the stored indicator, an access to a Translation Lookaside Buffer (TLB) when fetching an instruction from the target address during a first execution of the branch instruction;
• and
• suppressing, in response to the stored indicator, a second access to the TLB when fetching another instruction from the target address during a second execution of the branch instruction.

A processor comprising:

• an instruction cache operative to store instructions and pre-decode information;
• page residence detection logic included in a pre-decoder, the page residence logic operative to generate an indication that a target address of a branch instruction is located in a memory page that includes a branch instruction address associated with the branch instruction prior to storing the branch instruction in the instruction cache as the pre-decode information;
• and
• a Translation Lookaside Buffer (TLB) operative to generate memory access permission information upon instruction fetches, wherein access to the TLB is suppressed in response to detecting the indication in conjunction with fetching a particular instruction at the target address while executing the branch instruction.

A processor comprising:

• a memory interface operative to access memory external to the processor, wherein the memory is organized to include pages;
• a cache memory in data transfer relationship with the memory interface, the cache memory operative to store instructions;
• a pre-decoder interposed between the memory interface and the cache memory, the pre-decoder operative to calculate a target address of a branch instruction prior to storing the branch instruction in the cache memory, and further adapted to store pre-decode information in the cache memory, the pre-decode information indicative of whether the calculated target address is located in a logical page that includes the branch instruction;
• and
• a Translation Lookaside Buffer (TLB) operative to manage permission attributes associated with the pages, and wherein upon fetching a first instruction at the target address of the branch instruction during execution of the branch instruction, a particular permission attribute-checking access to the TLB is selectively suppressed in response to the pre-decode information.