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US 7,406,609 B2Granted
Method and apparatus for minimizing leakage current in semiconductor logic
AssigneeIntel Corporation
InventorsLawrence S. Uzelac, Andrew M. Volk
Life of this patent
Estimating the term…
Abstract
Leakage current in semiconductor logic can be minimized using the present systems and techniques. For example, a CMOS circuit for low leakage battery operation can connect a real time clock to the power supply when available or to a low leakage source when the power supply is not available.
Claims20
An apparatus comprising:
- a first circuit;
- and
- a second circuit that operates in a normal mode and in a low leakage mode, said low leakage mode providing a biasing condition that reduces a sub-threshold off current for the first circuit by raising transistor source node voltage levels for the first circuit.
A system comprising:
- logic means for performing computations;
- power supply means for operating the logic means in a first mode and in a second mode;
- and
- source-node-voltage-level modification means for providing a biasing condition to the logic means that minimizes leakage current in the second mode of operation of the logic means, wherein the source-node-voltage-level modification means comprises means for raising transistor source node voltage levels.
1 more element
A method comprising:
- operating a circuit from a primary voltage source during a first mode of operation;
- and
- operating the circuit from a secondary voltage source during a second mode of operation that minimizes leakage current and reduces a sub-threshold off current for the circuit by raising transistor source node voltage levels for the circuit.
Dependencies are inferred from the claim text.